本文關(guān)鍵詞：基于多核嵌入式HEVC解碼器并行優(yōu)化及實(shí)現(xiàn)　出處：《西南交通大學(xué)》2016年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： HEVC編解碼標(biāo)準(zhǔn) 解碼器 多核并行計(jì)算 ARM big.LITTLE

【摘要】：隨著移動(dòng)互聯(lián)網(wǎng)和多媒體的不斷發(fā)展,實(shí)時(shí)高清視頻通信越來越受到關(guān)注。HEVC為ITU-T(國際電信聯(lián)盟)和ISO(國際標(biāo)準(zhǔn)化組織)2013年聯(lián)合推出最新視頻編解碼標(biāo)準(zhǔn)。由于其壓縮率相較于H.264提高50%,網(wǎng)絡(luò)帶寬減少了一半,所以得到廣泛關(guān)注,但是,HEVC算法復(fù)雜度增加,實(shí)時(shí)編解碼對(duì)于硬件資源有限的移動(dòng)設(shè)備處理器帶來很大壓力。由于能耗問題的制約,現(xiàn)在大部分移動(dòng)設(shè)備使用能耗更低ARM架構(gòu)多核心處理器作為自己CPU,所以,在ARM多核心處理器通過并行計(jì)算HEVC提高解碼器性能成為一個(gè)熱點(diǎn)研究問題。首先,本文研究分析了最新HEVC編解碼標(biāo)準(zhǔn)相比于H.264的改進(jìn)之處,總結(jié)了解碼器的新特性,研究了最新ARM多核架構(gòu)處理器(Big.LITTLE)體系結(jié)構(gòu)及特性,分析此架構(gòu)的并行計(jì)算特點(diǎn)。然后,分析像素重構(gòu)(幀內(nèi)預(yù)測(cè)、幀間預(yù)測(cè)、反量化、反變換)過程數(shù)據(jù)耦合性,研究適合big.LITTLE架構(gòu)體系處理器并行粒度,本文選用重疊波前并行算法為像素重構(gòu)實(shí)現(xiàn)方案,以CTB行作為基本的并行粒度。其次,研究HEVC解碼器過程中環(huán)路濾波數(shù)據(jù)耦合性,分別研究去方塊濾波和樣點(diǎn)自適應(yīng)補(bǔ)償濾波的實(shí)現(xiàn)原理。去方塊濾波在實(shí)現(xiàn)并行化計(jì)算時(shí)先完成一幀圖像的垂直邊界濾波,再完成水平行邊界濾波,以CTB行和CTB列為并行基本粒度,樣點(diǎn)自適應(yīng)以CTB行或者列為并行基本粒度。為了提高cache命中率和線程在線率,本文的環(huán)路濾波并行過程將CTB列的去方塊濾波和樣點(diǎn)自適應(yīng)融合為一個(gè)并行任務(wù)。HEVC解碼器經(jīng)過本文的并行優(yōu)化設(shè)計(jì)和實(shí)現(xiàn),對(duì)高清(1280×720)和標(biāo)清(832×480)兩種測(cè)試序列實(shí)現(xiàn)了實(shí)時(shí)解碼,解碼幀率相對(duì)于串行解碼器有了明顯提高。
[Abstract]:With the continuous development of mobile Internet and multimedia, real-time high-definition video communication has attracted more and more attention. HEVC jointly launched the latest video coding and decoding standard for ITU-T (International Telecommunication Union) and ISO (International Standardization Organization) in 2013. Because its compression rate is increased by 50% compared with H.264, and the network bandwidth has been reduced by half, it has attracted wide attention. However, the complexity of HEVC algorithm increases, and real-time codec brings great pressure to the mobile device processors with limited hardware resources. Due to the restriction of energy consumption, most of the mobile devices consume less energy than the ARM architecture, and the multi-core processors of the CPU architecture are their own ARM. Therefore, it becomes a hot research topic to improve the decoder performance of ARM multi-core processors through parallel computing. First of all, this paper studies and analyzes the improvement of the latest HEVC encoding and decoding standard compared with H.264, summarizes the new characteristics of the decoder, studies the architecture and characteristics of the latest ARM multi-core architecture processor (Big.LITTLE), and analyzes the parallel computing characteristics of the architecture. Then, analysis of the reconstructed pixels (intra prediction, inter prediction, inverse quantization, inverse transform) process data coupling, research for the big.LITTLE architecture processor parallel granularity parallel algorithm using overlapping wavefront scheme for pixel reconstruction, using CTB as basic parallel granularity. Secondly, the coupling of the loop filter data in the HEVC decoder is studied, and the principle of the block filtering and the adaptive compensation filter is studied respectively. To achieve parallel computing, we first finish the vertical boundary filtering of a single image, and then perform the horizontal row boundary filtering. We use CTB row and CTB column as parallel basic granularity, and sample points are adaptive to row CTB or row as parallel basic granularity. In order to improve cache hit rate and thread online rate, the loop filtering parallel process in this paper integrates CTB block filter and sample adaptation into a parallel task. The HEVC decoder is designed and implemented through parallel optimization in this paper. It achieves real-time decoding for HD (1280 * 720) and standard (832 * 480) two test sequences, and the decoding frame rate has been significantly improved compared with the serial decoder.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN919.81

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