【摘要】：中子數(shù)字成像試驗(yàn)中,現(xiàn)場(chǎng)可編程門陣列(FPGA)是重要的成像邏輯控制器件。然而,中子輻照易引起FPGA的單粒子效應(yīng),對(duì)中子成像引入本底噪聲,因此必須采取措施,減少中子輻照對(duì)FPGA成像的影響。結(jié)合圖像周期性的特點(diǎn),采用三判二的技術(shù)方法替代三模冗余,裁決成像關(guān)鍵信號(hào);采用硬件實(shí)現(xiàn)的中值濾波算法,平滑由于RAM區(qū)單粒子翻轉(zhuǎn)等原因呈現(xiàn)在圖像上的噪點(diǎn)。仿真結(jié)果表明,本文采用的兩種技術(shù)方法不但降低資金成本,提高FPGA資源冗余度,而且在取得良好的抗輻照濾波效果的同時(shí),保留圖像細(xì)節(jié)。時(shí)序仿真和硬件平臺(tái)驗(yàn)證了設(shè)計(jì)的正確性。
[Abstract]:In the neutron digital imaging test, the field programmable gate array (FPGA) is an important imaging logic control device. However, the neutron irradiation is easy to cause the single particle effect of FPGA, and the neutron imaging is introduced to the background noise. Therefore, measures must be taken to reduce the effect of neutron irradiation on the imaging of FPGA. Combined with the characteristics of the periodicity of the image, a three judgment of two is adopted. The method replaces the three mode redundancy to adjudication the key signal of imaging, and uses the median filtering algorithm implemented by hardware to smooth the noise on the image because of the single particle flip of the RAM region. The simulation results show that the two methods used in this paper not only reduce the cost of capital, raise the redundancy of FPGA resources, but also obtain good radiation resistance. While preserving the image details, timing simulation and hardware platform verify the correctness of the design.
【作者單位】： 東北師范大學(xué)物理學(xué)院;中國(guó)科學(xué)院長(zhǎng)春光學(xué)精密機(jī)械與物理研究所;
【基金】：國(guó)家自然科學(xué)基金項(xiàng)目(11305034) 吉林省科技發(fā)展計(jì)劃項(xiàng)目(20150520084JH) 吉林省教育廳十二五科技項(xiàng)目(2014B042)
【分類號(hào)】：O571.53

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