本文選題：AES + 序列密碼��； 參考：《黑龍江大學(xué)》2015年碩士論文

【摘要】：2013年愛德華斯諾登棱鏡事件披露了美國(guó)國(guó)安局的監(jiān)聽丑聞,引起了世界的轟動(dòng)。人類信息的安全更加得到了重視,數(shù)據(jù)加密系統(tǒng)的形成也是在此情況下產(chǎn)生和發(fā)展起來(lái)的。加密算法的研究成為了一種前所未有的挑戰(zhàn)。2002年起,美國(guó)公布了最新的高級(jí)加密標(biāo)準(zhǔn)AES,它的出現(xiàn)得到了廣泛的推廣與應(yīng)用,因此研究AES算法加密是有很大的前景和價(jià)值。本文主要設(shè)計(jì)了一種基于FPGA的AES算法的加密方案,在硬件開發(fā)環(huán)境FPGA上實(shí)現(xiàn)數(shù)據(jù)的加密,該系統(tǒng)實(shí)現(xiàn)了數(shù)據(jù)的安全、無(wú)誤傳輸。本論文首先概述了AES算法的中所涉及的數(shù)學(xué)基礎(chǔ)知識(shí)及AES算法的原理,其次主要解析了AES加密算法的整體結(jié)構(gòu),對(duì)算法中的各子模塊進(jìn)行了分析,用Verilog語(yǔ)言來(lái)描述算法的硬件實(shí)現(xiàn)。與此同時(shí)給出了各個(gè)子模塊的原理圖及其仿真效果。本文在第三章中設(shè)計(jì)了基于FPGA的兩種加密算法,它們分別是分組密碼AES算法和序列密碼A5/1算法,加密算法的選取直接影響到整個(gè)加密系統(tǒng)的優(yōu)良,所以通過(guò)文獻(xiàn)的查閱,采用對(duì)比的方法選擇最優(yōu)算法。本章節(jié)還對(duì)AES和A5/1兩種算法在進(jìn)行大數(shù)據(jù)加密時(shí)吞吐量、資源占用率、功耗等進(jìn)行對(duì)比,最后選擇大數(shù)據(jù)加密更有優(yōu)勢(shì)的加密算法。本設(shè)計(jì)的難點(diǎn)在于采用FPGA硬件實(shí)現(xiàn)AES算法,以保護(hù)初始密鑰不被攻破和泄漏。同時(shí),在AES算法與A5/1算法的比較中需要進(jìn)行大量數(shù)據(jù)的采集,在采集前需要加入一個(gè)FIFO緩存模塊,在此模塊上要準(zhǔn)確控制時(shí)鐘的輸入才能保證數(shù)據(jù)正確傳輸。本文全部采用FPGA硬件平臺(tái)實(shí)現(xiàn)數(shù)據(jù)加密,硬件加密具有速度快速,安全性高的優(yōu)點(diǎn),是密碼學(xué)應(yīng)用的趨勢(shì)。
[Abstract]:The Edward Snowden Prism affair in 2013, which revealed the NSA surveillance scandal, caused a world sensation. More attention has been paid to the security of human information, and the formation of data encryption system is also produced and developed in this situation. The research of encryption algorithm has become an unprecedented challenge. Since 2002, the United States has published the latest advanced encryption standard AESs, which has been widely promoted and applied. Therefore, the research of AES encryption algorithm has great prospect and value. In this paper, an encryption scheme of AES algorithm based on FPGA is designed, which can encrypt the data on the hardware development environment FPGA. The system realizes the security and accurate transmission of the data. In this paper, the basic knowledge of AES algorithm and the principle of AES algorithm are summarized. Secondly, the whole structure of AES encryption algorithm is analyzed, and the sub-modules of the algorithm are analyzed. Verilog language is used to describe the hardware implementation of the algorithm. At the same time, the schematic diagram of each sub-module and its simulation effect are given. In the third chapter, we design two encryption algorithms based on FPGA, they are block cipher AES algorithm and sequence cipher A5 / 1 algorithm. The selection of encryption algorithm directly affects the quality of the whole encryption system. The optimal algorithm is chosen by contrast method. This chapter also compares the throughput, resource occupancy and power consumption of AES and A5 / 1 algorithms in big data encryption. The difficulty of this design is to use FPGA hardware to implement AES algorithm to protect the initial key from breaking and leaking. At the same time, in the comparison between AES algorithm and A5 / 1 algorithm, a large amount of data need to be collected, and a FIFO buffer module should be added before the acquisition. In this module, the clock input must be controlled accurately in order to ensure the correct transmission of data. This paper uses FPGA hardware platform to realize data encryption. Hardware encryption has the advantages of fast speed and high security. It is the trend of cryptography application.
【學(xué)位授予單位】：黑龍江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN918.4
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本文編號(hào)：1854902