發(fā)布時(shí)間：2018-03-16 17:22

  本文選題：鎖相環(huán)　切入點(diǎn)：寬輸入輸出頻率范圍　出處：《國(guó)防科學(xué)技術(shù)大學(xué)》2014年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著集成電路飛速發(fā)展,電子產(chǎn)品日新月異的更新給集成電路的設(shè)計(jì)提出了高速換代的要求。而模擬集成電路設(shè)計(jì)要遵循各性能參數(shù)相互制約的關(guān)系,這使的某一個(gè)性能參數(shù)非常好的時(shí)候,另一個(gè)性能參數(shù)卻可能成為短板,所以同時(shí)適用于不同性能指標(biāo)的模擬電路設(shè)計(jì)具有很大挑戰(zhàn)性。鎖相環(huán)作為模擬電路設(shè)計(jì)的一個(gè)典型代表,其在固定輸入輸出頻率時(shí)的低抖動(dòng)要求較容易實(shí)現(xiàn),但是當(dāng)輸入或輸出頻率變化時(shí),勢(shì)必會(huì)使某些固定的環(huán)路參數(shù)成為一個(gè)變化的量,使PLL系統(tǒng)成為一個(gè)動(dòng)態(tài)系統(tǒng),該系統(tǒng)對(duì)不同頻率輸出點(diǎn)的抖動(dòng)性能沒(méi)有一個(gè)很好的收斂性,所以寬輸入輸出頻率范圍的低抖動(dòng)鎖相環(huán)設(shè)計(jì)是一個(gè)難點(diǎn)。本文在40nm CMOS工藝下研究了寬輸入輸出頻率范圍鎖相環(huán)的低抖動(dòng)實(shí)現(xiàn),通過(guò)系統(tǒng)級(jí),行為級(jí)、電路級(jí)和版圖級(jí)的全方位研究,得到影響鎖相環(huán)輸出抖動(dòng)的三個(gè)主要因素:電源噪聲、壓控振蕩器控制電壓波動(dòng)和抖動(dòng)在整個(gè)輸出頻率范圍的不一致性。為了實(shí)現(xiàn)抖動(dòng)在整個(gè)輸出頻率范圍的一致性,本文改進(jìn)了常規(guī)的自適應(yīng)帶寬鎖相環(huán)架構(gòu),通過(guò)理論推導(dǎo),驗(yàn)證了該架構(gòu)帶寬和阻尼因子隨參考頻率的的變化可以自適應(yīng)。為了Vc電壓波動(dòng)的抑制,本文從鎖相環(huán)行為級(jí)分析了鑒頻鑒相器和電荷泵的非理想因素,在此基礎(chǔ)上改進(jìn)了鑒頻鑒相器和電荷泵的電路結(jié)構(gòu)。驗(yàn)證結(jié)果表明鎖相環(huán)在鎖定狀態(tài)下,本文采用的設(shè)計(jì)使壓控振蕩器控制信號(hào)上的峰峰值從2.1mV下降到0.13mV,下降了一個(gè)多數(shù)量級(jí)。為了抑制電源噪聲對(duì)鎖相環(huán)輸出抖動(dòng)的影響,本文從鎖相環(huán)外部設(shè)計(jì)了低壓差穩(wěn)壓器,實(shí)現(xiàn)弱噪聲電源供電;然后對(duì)壓控振蕩器等模塊進(jìn)行了高電源抑制比的設(shè)計(jì)。驗(yàn)證結(jié)果表明本文的設(shè)計(jì)策略使電源上10%的噪聲被衰減到不足0.5%。本文最后實(shí)現(xiàn)了一款40nm工藝下的寬輸入輸出頻率范圍低抖動(dòng)鎖相環(huán),并設(shè)計(jì)了版圖和測(cè)試芯片。通過(guò)電路與版圖的仿真結(jié)果和文獻(xiàn)中的PLL仿真結(jié)果對(duì)比,本文所設(shè)計(jì)的PLL抖動(dòng)非常低,10000個(gè)周期的周期周期峰峰值抖動(dòng)只有不到1%,RMS抖動(dòng)也只有1.2‰,超過(guò)了文獻(xiàn)中同類(lèi)型的PLL。并且該P(yáng)LL的抖動(dòng)一致性較好,實(shí)現(xiàn)了寬輸入輸出頻率范圍高性能PLL的要求。
[Abstract]:With the rapid development of integrated circuits, the rapid updating of electronic products has put forward the requirement of high-speed replacement for the design of integrated circuits. This makes one of the performance parameters very good, while the other performance parameter can become a short plate, Therefore, it is very challenging to design analog circuits with different performance indexes. As a typical example of analog circuit design, the low jitter requirement of PLL in fixed input and output frequency is easy to realize. However, when the input or output frequency changes, some fixed loop parameters will become a variable, and the PLL system will become a dynamic system. The system does not have a good convergence to the jitter performance of different frequency output points. Therefore, the design of low jitter PLL with wide input and output frequency range is a difficulty. In this paper, the low jitter realization of PLL with wide input and output frequency range is studied in 40nm CMOS process, which is implemented at system level and behavior level. By studying the circuit level and layout level, three main factors affecting the output jitter of the PLL are obtained: power noise, Voltage controlled oscillator controls the inconsistency of voltage fluctuation and jitter in the whole output frequency range. In order to realize the consistency of jitter in the whole output frequency range, the conventional adaptive bandwidth PLL architecture is improved in this paper. It is verified that the variation of bandwidth and damping factor with reference frequency is adaptive. In order to suppress the voltage fluctuation of VC, the non-ideal factors of phase discriminator and charge pump are analyzed from the behavior level of phase-locked loop. The circuit structure of the phase discriminator and the charge pump is improved. The results show that the PLL is in the locked state. The design adopted in this paper reduces the peak and peak value of the VCO control signal from 2.1 MV to 0.13 MV, which is a multi-order of magnitude decrease. In order to suppress the influence of power noise on the output jitter of PLL, a low-voltage differential regulator is designed from the outside of PLL. Realize the power supply of weak noise power supply; Then the VCO and other modules are designed with high PSRR. The verification results show that the design strategy of this paper makes the noise of 10% in the power supply attenuated to less than 0.5. Finally, a 40nm wide input transmission is realized in this paper. Out of frequency range low jitter PLL, The layout and test chip are designed. Compared with the simulation results of the circuit and layout and the PLL simulation results in the literature, the PLL jitter designed in this paper is very low. The jitter consistency of the PLL is better than that of the same type of PLLs in the literature, and the requirement of high performance PLL with wide input and output frequency range is achieved.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN911.8
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本文編號(hào)：1620893