本文選題：軟件無(wú)線電　切入點(diǎn)：FPGA數(shù)字信號(hào)處理　出處：《哈爾濱工業(yè)大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：近些年來(lái),隨著FPGA(Field Programmable Gate Array)數(shù)字信號(hào)處理技術(shù)及軟件無(wú)線電的飛速發(fā)展,FPGA在通信領(lǐng)域的應(yīng)用受到了越來(lái)越多的關(guān)注。針對(duì)這一點(diǎn),本文以FPGA為主要數(shù)字信號(hào)處理器件,研制了一個(gè)無(wú)線通信信號(hào)解調(diào)實(shí)驗(yàn)平臺(tái)。無(wú)線通信可以分為兩大類(lèi):單用戶多制式無(wú)線通信,如AM(Amplitude Modulation)、FM(Frequency Modulation)等;單制式多用戶無(wú)線通信,如CDMA(Code Division Multiple Access)、TD-LTE(Time Division Long Term Evolution)等。為了能了解和掌握調(diào)制解調(diào)的FPGA實(shí)現(xiàn),在第一類(lèi)中選取了FM、AM(模擬調(diào)制)、2ASK、2FSK(數(shù)字調(diào)制)四種作為解調(diào)的實(shí)例,并采用歸一化瞬時(shí)幅度特征,分別在模擬調(diào)制和數(shù)字調(diào)制中來(lái)實(shí)現(xiàn)調(diào)制模式的識(shí)別,另外考慮到不同數(shù)字調(diào)制方式的解調(diào),其FPGA實(shí)現(xiàn)已被廣泛研究,因此僅研究數(shù)字調(diào)制解調(diào)中的難點(diǎn),載波同步技術(shù)的FPGA實(shí)現(xiàn)。在第二類(lèi)中選取了CDMA擴(kuò)頻系統(tǒng)作為解調(diào)實(shí)例。同時(shí)完成了一個(gè)包含射頻前端硬件電路和后端數(shù)字信號(hào)處理的硬件實(shí)驗(yàn)平臺(tái)。射頻前端電路,采用超外差接收結(jié)構(gòu),完成對(duì)天線接收到的信號(hào)的兩次下變頻處理及自動(dòng)增益控制,最終在自動(dòng)增益控制的輸出端可得到一個(gè)455k Hz的調(diào)頻信號(hào);數(shù)字信號(hào)處理電路,采用A/D采樣量化、FPGA上運(yùn)行算法、D/A將解調(diào)的數(shù)據(jù)輸出的方式,來(lái)運(yùn)行各種FPGA調(diào)制解調(diào)算法。將FM信號(hào)的解調(diào)算法在后端數(shù)字信號(hào)處理板上運(yùn)行,結(jié)合射頻前端,能聽(tīng)到清楚的調(diào)頻廣播。載波同步采用Costas環(huán)來(lái)完成,在第二級(jí)乘法器中,用一種極其節(jié)省資源的近似處理來(lái)完成乘法,仿真結(jié)果表明,在輸入頻差在0-100k Hz范圍內(nèi),均能實(shí)現(xiàn)鎖定,性能良好。調(diào)制模式識(shí)別特征的FPGA實(shí)現(xiàn),采用FFT(Fast Fourier Transformation)IP(Intellectual Property)核,結(jié)合多級(jí)流水線實(shí)現(xiàn)累加及控制狀態(tài)機(jī)完成,在Modelsim中的仿真結(jié)果表明,不同制式的信號(hào)FFT的冪指數(shù)部分相差32倍,能有效的完成調(diào)制模式識(shí)別。在MMSE(Minimum Mean Square Error)多用戶檢測(cè)(Multiuser Detection,MUD)算法的FPGA實(shí)現(xiàn)中,本文采用PC機(jī)Matlab通過(guò)RS232給FPGA發(fā)送數(shù)據(jù)的方式,來(lái)完成算法FPGA實(shí)現(xiàn)的蒙特卡洛仿真。所得到的誤碼率,在匹配濾波和MMSE多用戶檢測(cè)算法的理論值之間,考慮到量化和截?cái)嗨鸬恼`差,認(rèn)為該算法在FPGA中實(shí)現(xiàn)是正確的。
[Abstract]:In recent years, with the rapid development of digital signal processing technology and software radio technology of FPGA(Field Programmable Gate, the application of FPGA in the field of communication has attracted more and more attention. In this paper, FPGA is used as the main digital signal processing device. A wireless communication signal demodulation experimental platform is developed. Wireless communication can be divided into two categories: single user multi-mode wireless communication, such as AM(Amplitude Modulation / FM Frequency Modulation, single-mode multi-user wireless communication, For example, CDMA(Code Division Multiple access / TD-LTEtime Division Long Term Evolution. In order to understand and master the FPGA implementation of modulation and demodulation, four kinds of FM AM (Analog Modulation 2ASK ~ 2FSKK) are selected as examples of demodulation, and normalized instantaneous amplitude characteristics are adopted. In order to realize modulation pattern recognition in analog modulation and digital modulation respectively, and considering the demodulation of different digital modulation methods, the FPGA implementation has been widely studied, so only the difficulties in digital modulation and demodulation are studied. FPGA implementation of carrier synchronization technology. In the second category, the CDMA spread spectrum system is selected as an example of demodulation. At the same time, a hardware experimental platform including RF front-end hardware circuit and back-end digital signal processing is completed. Using the superheterodyne receiving structure, two downconversion processing and automatic gain control of the signals received by the antenna are completed. Finally, an FM signal of 455kHz can be obtained at the output end of the automatic gain control, the digital signal processing circuit, the digital signal processing circuit, the digital signal processing circuit, the digital signal processing circuit, the digital signal processing circuit, In this paper, we run various FPGA modulation and demodulation algorithms by using the arithmetic of D / A to output the demodulated data on the Ar / D sampling quantized FPGA. The demodulation algorithm of FM signal is run on the back-end digital signal processing board, combined with the RF front-end, and the demodulation algorithm of the FM signal is used in the back-end digital signal processing board. The frequency modulation broadcast can be heard clearly. The carrier synchronization is accomplished by Costas loop. In the second stage multiplier, a resource-saving approximate processing is used to complete the multiplication. The simulation results show that the input frequency difference is in the range of 0-100kHz. The FPGA realization of modulation pattern recognition features is realized by FFT(Fast Fourier Transformation)IP(Intellectual property core, combined with multistage pipeline to realize the accumulation and control state machine. The simulation results in Modelsim show that, The difference of power exponent of different FFT is 32 times, which can effectively realize modulation pattern recognition. In the FPGA implementation of MMSE(Minimum Mean Square error multiuser detection algorithm, this paper uses PC Matlab to send data to FPGA via RS232. The error rate of the algorithm is correct in FPGA, considering the error caused by quantization and truncation between the theoretical values of the matched filter and the MMSE multiuser detection algorithm.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN92;TN911.3

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本文編號(hào)：1597791