本文關(guān)鍵詞：電源噪聲引起CMOS鎖相環(huán)的周期抖動(dòng)研究　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 電源噪聲 鎖相環(huán) 周期抖動(dòng)

【摘要】：抖動(dòng)的大小作為衡量信號(hào)完整性的一個(gè)技術(shù)指標(biāo),而電源噪聲是時(shí)序抖動(dòng)的最重要的成因。在電源完整性方面,通過提供一個(gè)穩(wěn)定的電源分配網(wǎng)絡(luò)(PDN)來最大限度的減小電源噪聲,以此達(dá)到減小時(shí)序抖動(dòng)的目的。但是,在高速的系統(tǒng)中封裝呈現(xiàn)出很大電感性,因此我們?cè)O(shè)計(jì)PDN時(shí)不可能將OI/接口產(chǎn)生的電源噪聲忽略不計(jì)。鎖相環(huán)作為serdes電路,頻率合成器中的時(shí)序最敏感模塊,所以我們很有必要對(duì)鎖相環(huán)系統(tǒng)中的電源噪聲和抖動(dòng)的關(guān)系進(jìn)行深入研究。本文首先介紹了電源噪聲對(duì)電子系統(tǒng)的影響以及對(duì)電源分配網(wǎng)絡(luò)模型進(jìn)行了講解以減小電源噪聲;又對(duì)抖動(dòng)進(jìn)行了系統(tǒng)的闡述,主要介紹了相位抖動(dòng),周期抖動(dòng)以及周期間抖動(dòng)之間的關(guān)系;闡述了鎖相環(huán)電路的發(fā)展及結(jié)構(gòu),并對(duì)傳統(tǒng)的用于教學(xué)的鎖相環(huán)電路結(jié)構(gòu)的每個(gè)模塊進(jìn)行了改進(jìn),用Hspice建立此鎖相環(huán)的模型,并且通過眼圖對(duì)抖動(dòng)的大小進(jìn)行度量,使在無電源噪聲的情況下,鎖相環(huán)的自身的抖動(dòng)足夠低,以使增加此鎖相環(huán)的可靠性及可用性。通過給此改進(jìn)的鎖相環(huán)電路加不同頻率的電源噪聲(電源噪聲的幅值不變),研究不同電源噪聲頻率下抖動(dòng)和電源噪聲的關(guān)系。目前已經(jīng)有一些關(guān)于抖動(dòng)的建模以及環(huán)形振蕩器的相位噪聲研究。抖動(dòng)的模型得到的是環(huán)形振蕩器的抖動(dòng)和相位噪聲的表達(dá)式,但是,環(huán)形振蕩器的分析可能不適合于鎖相環(huán),因?yàn)殒i相環(huán)的影響因素多于環(huán)形振蕩器。還有一種基于宏模型的鎖相環(huán)的快速準(zhǔn)確的分析,盡管它可以減少分析噪聲影響時(shí)仿真的復(fù)雜性,但是當(dāng)鎖相環(huán)的結(jié)構(gòu)被改變時(shí)宏模型不得不被重新建立。另外一種方法是假設(shè)抖動(dòng)響應(yīng)是電源噪聲的線性函數(shù)的前期下,抖動(dòng)的靈敏度是一種有效的手段用于表征電源噪聲引起的抖動(dòng),但是抖動(dòng)靈敏度瞬態(tài)分析是非常耗時(shí)的,為了節(jié)省仿真時(shí)間,雖然提出了能快速得到抖動(dòng)的靈敏度曲線的方法。但是,不銜接的問題阻礙了它的應(yīng)用。相位抖動(dòng),周期抖動(dòng)與周期間抖動(dòng)是對(duì)抖動(dòng)的不同定義,我們研究發(fā)現(xiàn)周期抖動(dòng)和電源噪聲存在更好的線性關(guān)系�；谶@種線性關(guān)系,求出了周期抖動(dòng)和混合頻率下的電源噪聲的線性的關(guān)系表達(dá)式,利用這個(gè)表達(dá)式,可以預(yù)測(cè)電源噪聲引起的鎖相環(huán)的周期抖動(dòng)。利用所求的表達(dá)式計(jì)算得到的抖動(dòng)值和利用hspice仿真測(cè)量的抖動(dòng)值進(jìn)行對(duì)比,驗(yàn)證表達(dá)式的正確性及可用性。最后,文章還討論了壓控振蕩器控制電壓對(duì)鎖相環(huán)整個(gè)系統(tǒng)的抖動(dòng)的影響。
[Abstract]:The size of the jitter as a technical measure of signal integrity, and power supply noise is the important cause of timing jitter. In power integrity, by providing a stable power distribution network (PDN) to reduce the noise of power, in order to achieve the purpose of decreasing order jitter. However, in high speed system package shows great inductive power supply noise, so we design PDN OI/ interface will not be produced negligible. The PLL frequency synthesizer circuit as SerDes timing, the most sensitive module, so it is necessary for us to study the relationship of PLL system in power supply noise and jitter. This paper first introduces the influence of noise on the power electronic system and the power distribution network model are introduced to reduce the noise of power; and makes a systematic exposition of the main jitter. Introduces the relationship between phase jitter, cycle jitter and cycle cycle jitter; expounds the development and structure of PLL circuit for each module and the traditional teaching of the PLL circuit structure was improved, the establishment of PLL model with Hspice, measure and through the eye diagram of jitter size, make in the absence of power supply noise, PLL's jitter is low enough, in order to increase the reliability and usability of the PLL. The power supply noise by phase-locked loop circuit to improve the different frequency (amplitude and power supply noise does not change), study the different power supply noise frequency jitter and noise power relationship at present there have been some modeling about jitter and ring oscillator phase noise research. Jitter model is derived, jitter and phase noise of ring oscillator but ring oscillator The analysis may not be suitable for phase locked loop PLL, because of the impact factor than the ring oscillator. There is also a macro model based on phase locked loop of fast and accurate analysis, although it can reduce the complexity of the simulation analysis of the influence of noise, but when the PLL structure is changed when the macro model had to be re established. Another method is that the response is a linear function of the jitter of the power supply noise, jitter sensitivity is an effective means for the characterization of the power supply noise caused by jitter, but the jitter sensitivity of the transient analysis is very time-consuming, in order to save simulation time, although the proposed method can quickly obtain the sensitivity curve of jitter. However, no connection the problems that hinder its application. The phase jitter, cycle jitter and jitter during the week is different definitions of jitter, we found that the cycle jitter and noise power There is a linear relationship between the sound better. This linear relationship based on the calculated formulas of the linear power supply noise jitter and mixed frequency of the use of this expression can predict the periodic jitter phase locked loop. The power supply noise caused by HSPICE simulation and the measured jitter value comparison value calculated by the formula for the jitter, correctness and usability validation expression. Finally, the influence of the VCO control voltage of PLL jitter of the system is discussed.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.8

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