本文關(guān)鍵詞：TD-LTE基站物理層下行鏈路設(shè)計與實現(xiàn)　出處：《中國科學(xué)技術(shù)大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： TD-LTE 物理層下行鏈路 RapidIO OFDM MIMO

【摘要】：隨著科技發(fā)展和人類需求不斷增長,移動通信已經(jīng)完成了三次變革,目前正在進(jìn)行第四次變革,相比3G,第四次變革演進(jìn)了無線接入技術(shù)和網(wǎng)絡(luò)架構(gòu),它的特點是寬帶和多功能集成。第四次變革以LTE(長期演進(jìn)計劃)為標(biāo)志,LTE是2006年以來3GPP啟動的最大新技術(shù)研發(fā)項目,被稱作“準(zhǔn)4G”技術(shù),包括FDD LTE和TDD LTE兩種不同模式,兩者主要區(qū)別在于FDD為頻分雙工,而TDD為時分雙工。2008年LTE Release8發(fā)布以后,各國都加緊研制和部署LTE設(shè)備,目前很多國家和地區(qū)已經(jīng)部署了LTE商用網(wǎng)絡(luò)；我國也于2013年12月頒布了TD-LTE牌照,標(biāo)志著我國正式進(jìn)入4G時代。作為全球性的4G標(biāo)準(zhǔn),LTE具有廣闊的市場前景。LTE無線接入網(wǎng)分為物理層、數(shù)據(jù)鏈路層和RRC層。物理層處于整個協(xié)議的最下層,是無線通信系統(tǒng)的基礎(chǔ),上層數(shù)據(jù)的正常傳輸和傳輸速率等均依賴于物理層。相比3G, LTE顯著提高了頻譜效率和峰值傳輸速率等,這主要得益于LTE物理層引入OFDM和MIMO等無線技術(shù),所以研究LTE物理層具有重要意義。 本論文主要研究TD-LTE基站物理層下行鏈路,包括物理層下行鏈路仿真平臺設(shè)計、基帶處理單元芯片間Serial RapidIO高速總線FPGA側(cè)實現(xiàn)、物理層下行鏈路DSP實現(xiàn)和典型信令流程驗證。主要研究工作和創(chuàng)新點包括： (1)設(shè)計并實現(xiàn)TD-LTE物理層下行鏈路matlab仿真平臺。本仿真平臺具備以下功能：下行各物理信道和物理信號發(fā)送、接收功能,支持各種系統(tǒng)帶寬,支持普通CP和擴展CP模式,支持單天線接收單天線發(fā)送、發(fā)射分集和空分復(fù)用MIMO模式,最大發(fā)送接收天線數(shù)為2X2等。其中發(fā)送部分通過Agilent89600VSA驗證正常,整個仿真平臺發(fā)送接收功能測試正常。研究主要算法并對下行各物理信道進(jìn)行性能仿真和算法改進(jìn),目前PCFICH、PDCCH接收誤碼率測試結(jié)果滿足LTE規(guī)范要求,PBCH、PDSCH接收誤碼率測試結(jié)果比LTE規(guī)范差,還需進(jìn)一步改進(jìn)。 (2)在FPGA上實現(xiàn)單lane3.125Gbps的Serial RapidIO。由于LTE的多天線、高帶寬特性,基帶處理單元使用Hyplink和Serial RapidIO來滿足其上各芯片之間的高速率數(shù)據(jù)傳輸要求。本論文通過研究RapidIO協(xié)議標(biāo)準(zhǔn)包括RapidIO物理層、傳輸層、邏輯層、GTP、鏈路初始化等,在FPGA上實現(xiàn)了單lane3.125Gbps的Serial RapidIO,經(jīng)過chipscope等測試工具測試工作正常。 (3)在以TMS320C6670為核心器件的基帶處理單元上實現(xiàn)了TD-LTE物理層下行鏈路并對其進(jìn)行了驗證。研究TMS320C6670DSP芯片并使用其內(nèi)部FFTC、BCP等協(xié)處理器實現(xiàn)TD-LTE物理層下行鏈路,通過natlab仿真平臺和Agilent89600VSA對下行鏈路DSP實現(xiàn)進(jìn)行驗證,驗證結(jié)果表明各信道能夠正常工作。 (4)學(xué)習(xí)LTE開機附著流程并基于下行鏈路進(jìn)行信令流程調(diào)測,由于LTE信令流程正確執(zhí)行需要各協(xié)議層配合完成,本論文提出了數(shù)據(jù)打樁技術(shù),通過數(shù)據(jù)打樁技術(shù)在僅有物理層下行鏈路的情況下成功進(jìn)行了UE開機附著流程前幾步的驗證。數(shù)據(jù)打樁技術(shù)可以加快項目開發(fā)進(jìn)度,在開發(fā)TD-LTE基站設(shè)備過程中,我們采用數(shù)據(jù)打樁技術(shù)實際調(diào)測開機附著信令流程比傳統(tǒng)串行開發(fā)調(diào)試方法節(jié)省了近一半時間。
[Abstract]:With the development of science and technology and human growing demand for mobile communications, has completed the three revolution, is currently fourth times change, compared to 3G, fourth times change the evolution of wireless access technology and network architecture, it is characterized by wide band and multi-function integration. The fourth revolution in LTE (long term evolution) as a symbol, LTE since 2006, 3GPP started the biggest new technology research and development project, known as the "4G" technology, including two different models of FDD LTE and TDD LTE, the major difference between the two is FDD for frequency division duplex, TDD.2008 LTE Release8 for TDD years after the release, all countries are stepping up the development and deployment of LTE equipment, at present a lot of countries and regions have deployed LTE commercial network; China in December 2013 issued TD-LTE licenses, marking China's formal entry into the 4G era. As a global 4G standard, LTE has a broad market prospect of.LTE Wireless access network is divided into physical layer, data link layer and the RRC layer. The underlying physical layer in the whole of the agreement, is the basis of the wireless communication system, the data of normal transmission and transmission rate are dependent on the physical layer. Compared with 3G, LTE significantly improves the spectrum efficiency and peak transmission rate, the main thanks to the introduction of OFDM and MIMO wireless technology to the LTE physical layer, so the research of LTE physical layer has important significance.
This paper mainly studies the TD-LTE base station downlink physical layer downlink simulation platform, including physical layer design, baseband processing unit chip Serial RapidIO high speed bus FPGA side, the physical layer downlink DSP and typical signaling process validation. The main research work and innovation include:
(1) the design and implementation of TD-LTE matlab physical layer downlink simulation platform. This simulation platform has the following functions: send the downlink physical channel and the physical signal receiving function, support a variety of system bandwidth, supports CP and extended CP model, support single antenna receiving single antenna transmission, transmit diversity and spatial multiplexing MIMO model, maximum sending and receiving antenna number is 2X2. The sending section verified by Agilent89600VSA normal, the simulation platform of sending and receiving function test normal. And the main algorithm of the downlink physical channel performance simulation and algorithm improvement, the PCFICH, PDCCH BER test results meet the requirements of LTE, PBCH, PDSCH BER Test Results than the LTE specification is bad, needs to be further improved.
(2) lane3.125Gbps Serial single RapidIO. due to multi antenna LTE in FPGA, high bandwidth characteristics, baseband processing unit using Hyplink and Serial RapidIO to meet the requirements of the between each chip high speed data transmission. Through the study on RapidIO protocol including RapidIO physical layer, transport layer, logic layer, GTP. Link initialization, FPGA to achieve a single lane3.125Gbps Serial RapidIO, after chipscope testing tool to test the normal work.
(3) in the TMS320C6670 as the core component of the baseband processing unit is realized on the TD-LTE physical layer downlink and verified it. Research of TMS320C6670DSP chip and its internal FFTC, BCP coprocessor to achieve the TD-LTE physical layer downlink simulation platform was verified by natlab and Agilent89600VSA on the downlink of DSP implementation, verification results show that the channel be able to work properly.
(4) the learning process and based on the LTE boot attached for downlink signaling flow test, because the LTE signaling process needs correct execution of each layer with the completion of this thesis presents data piling technology, through the data piling technology in physical layer downlink only under the condition of the success of the UE boot attached verification process of the first few steps. The piling technology can accelerate the progress of project development, in the development of TD-LTE base station equipment in the process, we use the data piling technique actually tested the signaling process than the traditional serial attached boot debug method can save nearly half the time.

【學(xué)位授予單位】：中國科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN929.5

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 馮川;李小文;;LTE終端小區(qū)選擇方案設(shè)計及實現(xiàn)[J];電訊技術(shù);2010年03期

2 張曉丹;楊波;蘇曦;;LTE系統(tǒng)中eNodeB測試方案探討[J];電信技術(shù);2009年11期

3 李文宇;;基于SAE/LTE項目未來移動通信系統(tǒng)的長期演進(jìn)[J];電信科學(xué);2007年09期

4 房秉毅;張云勇;;LTE/LTE-A技術(shù)及標(biāo)準(zhǔn)進(jìn)展[J];電信網(wǎng)技術(shù);2010年05期

5 李穎,謝顯中,王新梅;空時碼綜述[J];電子與信息學(xué)報;2002年12期

6 羅一靜;段紅光;;利用TTCN進(jìn)行協(xié)議測試的一種方法[J];廣東通信技術(shù);2006年06期

7 鄧也;董鑫;王李勇;;TD-SCDMA基站池方案探討[J];電信工程技術(shù)與標(biāo)準(zhǔn)化;2010年07期

8 劉璇;;LTE測試,眾廠商齊頭并進(jìn)[J];國外電子測量技術(shù);2012年07期

9 華舒揚;黃芝平;;TMS320C6670的無線基帶信號處理系統(tǒng)設(shè)計[J];單片機與嵌入式系統(tǒng)應(yīng)用;2013年08期

10 章樂;李雅靜;倪明;柴小雨;;一種基于RapidIO接口的嵌入式系統(tǒng)[J];計算機工程;2008年S1期

，

本文編號：1385302