【摘要】：隨著現(xiàn)代數(shù)字信號處理向大容量數(shù)據(jù)、高速實時計算發(fā)展,高速、高性能計算及其實現(xiàn)手段成為近代數(shù)學(xué)和信息處理技術(shù)的重要命題。傳統(tǒng)的單核處理系統(tǒng)已經(jīng)難以滿足龐大的信息處理量和復(fù)雜信號的處理。多核芯片技術(shù)的產(chǎn)生,為解決這一問題提供了有效解決方案,并得到了業(yè)界廣泛的認(rèn)可。特別是集成了多種體系結(jié)構(gòu)和不同功能的處理器核的異構(gòu)多核系統(tǒng),可以將不同的計算任務(wù)分配給不同的處理器核并行處理,通過異構(gòu)計算單元加速任務(wù)執(zhí)行,能夠為多種應(yīng)用提供更加靈活、高效的處理機制,滿足多種應(yīng)用需求,成為未來多核技術(shù)主要發(fā)展方向之一。隨著復(fù)雜信號高性能、高密度計算需求的日益膨脹,傳統(tǒng)的將計算任務(wù)映射在多核系統(tǒng)中不同的處理核上,已難以滿足高速實時處理的要求。因此,多核和加速器形式的架構(gòu)應(yīng)運而生,一些多核處理器集成了定制的加速核來加速特定的應(yīng)用,但其靈活性不高。隨著可重構(gòu)技術(shù)的出現(xiàn),將可重構(gòu)計算技術(shù)應(yīng)用于硬件加速器中,能夠彌補通用運算與軟件計算在性能和靈活性上的鴻溝,為復(fù)雜高速信號的處理提供更高性能的平臺。本文針對上述問題,進行了有關(guān)可重構(gòu)計算技術(shù)和異構(gòu)多核系統(tǒng)中硬件加速器的研究。論文的主要工作如下：首先,本文針對應(yīng)用需求特征,提煉面向高密度計算的應(yīng)用特征和部分算法特征,分析出可重用程度高、可有效提高系統(tǒng)性能的計算類型,并對這些運算類型的算法進行了分析和優(yōu)化,提出了改進的矩陣求逆算法、函數(shù)擬合算法和針對算法的硬件架構(gòu)。其次,本文在優(yōu)化算法和結(jié)構(gòu)的基礎(chǔ)上,設(shè)計了一款面向異構(gòu)多核系統(tǒng)的可重構(gòu)硬件加速引擎,該硬件加速引擎主要面向高密度計算領(lǐng)域中矩陣類運算。特別是矩陣求逆運算,能夠高效地完成16階、32階、64階、128階單精度實數(shù)矩陣求逆運算。此外,在不增加運算和存儲資源的情況下,重構(gòu)了擬合和多目運算,豐富了該可重構(gòu)硬件加速引擎的功能。最后,本文對設(shè)計的硬件加速引擎進行了實驗測試和性能分析,并介紹了該硬件加速引擎在異構(gòu)多核系統(tǒng)中的集成,驗證了所設(shè)計的硬件加速引擎具有較高的性能。
[Abstract]:With the development of modern digital signal processing to large capacity data and high speed real-time computing, high speed, high performance computing and its means of implementation have become an important proposition of modern mathematics and information processing technology. The traditional single-core processing system has been difficult to meet the huge amount of information processing and complex signal processing. The emergence of multi-core chip technology provides an effective solution to solve this problem, and has been widely recognized by the industry. In particular, heterogeneous multicore systems with different architectures and different functions can assign different computing tasks to different processor cores for parallel processing, and speed up task execution through heterogeneous computing units. It can provide more flexible and efficient processing mechanism for many applications and meet the needs of many applications. It will become one of the main development directions of multi-nuclear technology in the future. With the high performance of complex signals and the increasing demand for high-density computing, the traditional mapping of computing tasks to different processing cores in multi-core systems is difficult to meet the requirements of high-speed real-time processing. Therefore, multicore and accelerator architectures emerge as the times require. Some multicore processors integrate custom accelerated cores to accelerate specific applications, but their flexibility is not high. With the advent of reconfigurable technology, the application of reconfigurable computing technology to hardware accelerators can bridge the gap between general computing and software computing in performance and flexibility, and provide a higher performance platform for complex high-speed signal processing. In this paper, the reconfigurable computing techniques and hardware accelerators in heterogeneous multicore systems are studied. The main work of this paper is as follows: firstly, according to the characteristics of application requirements, this paper abstracts the application features and some algorithm features for high-density computing, and analyzes the computing types with high degree of reuse, which can effectively improve the performance of the system. The algorithms of these types of operations are analyzed and optimized, and an improved matrix inverse algorithm, a function fitting algorithm and a hardware architecture for the algorithm are proposed. Secondly, based on the optimization algorithm and structure, a reconfigurable hardware acceleration engine for heterogeneous multi-core systems is designed. The hardware acceleration engine is mainly oriented to matrix operations in the field of high-density computing. Especially, the inverse operation of matrix can efficiently perform the inverse operation of 16, 32, 64 and 128 order of real matrix with single precision. In addition, the refactoring of fitting and multi-eye operation without adding computing and storage resources enriches the function of the reconfigurable hardware acceleration engine. Finally, the hardware acceleration engine is tested and its performance is analyzed, and the integration of the hardware acceleration engine in heterogeneous multi-core system is introduced. It is verified that the designed hardware acceleration engine has high performance.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TP301.6
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本文編號：2338314