本文關鍵詞： 圖像壓縮 FPGA JPEG　出處：《中北大學》2017年碩士論文　論文類型：學位論文

【摘要】：隨著數(shù)碼相機等電子產(chǎn)品滲透在人類生活的方方面面,以及圖像技術在航天、通訊、生物醫(yī)學等領域的不斷應用,這些廣大的需求刺激著圖像壓縮技術的發(fā)展。從JPEG壓縮到JPEG2000,再到JPEG XR,科研工作者對圖像壓縮的研究從未停止腳步。雖然JPEG2000和JPEG XR在某些性能方面優(yōu)于JPEG壓縮技術,但事實上,JPEG壓縮仍然是事實上的主流技術。同時,鑒于FPGA的快速發(fā)展與廣泛應用,它豐富的資源優(yōu)勢及它強大的并行優(yōu)勢越來越受到人們的青睞,因此,在很多對速度和實時性要求較高的應用中,科研人員更趨向用FPGA來實現(xiàn)圖像壓縮。鑒于JPEG壓縮在各領域的應用多是灰度圖像,因此本文實現(xiàn)的JPEG壓縮器是針對灰度圖像進行設計的。本文首先介紹了圖像壓縮的研究背景與意義以及目前JPEG壓縮的發(fā)展現(xiàn)狀,然后給出了JPEG編碼器在FPGA中實現(xiàn)的設計方案,并對本設計采用的JPEG壓縮基本系統(tǒng)的流程進行了詳盡的介紹。其次,又針對JPEG壓縮中重要的算法DCT變換和量化給出了新的實現(xiàn)方式,并用MATLAB對其做了仿真驗證。接著按模塊化的思想一一介紹了各個模塊在FPGA中的設計實現(xiàn),最后給出了各模塊的測試驗證。本設計采用Altera公司Cyclone III系列的芯片,在QuartusII 13.0的開發(fā)環(huán)境下完成設計。對二維DCT變換模塊,采用了類陳氏算法,充分利用FPGA的并行性和乘法器資源,實現(xiàn)了快速、穩(wěn)定的DCT變換。量化模塊創(chuàng)新的實現(xiàn)了可在FPGA中進行9級不同量化表的選擇,以查找表的方式實現(xiàn)了DC/AC系數(shù)的熵編碼。并先后對各個模塊進行了功能測試,將圖像源數(shù)據(jù)做成MIF文件進行測試,并用第三方軟件解碼,最后證明能夠顯示完整的圖片。測試結(jié)果表明,該JPEG編碼器實現(xiàn)了預期的功能,達到設計目標。
[Abstract]:With the penetration of digital cameras and other electronic products in all aspects of human life, as well as image technology in aerospace, communications, biomedical and other fields of continuous application. These vast demands stimulate the development of image compression technology, from JPEG compression to JPEG2000 to JPEG XR. Researchers have never stopped studying image compression. Although JPEG2000 and JPEG XR are better than JPEG compression in some aspects, in fact. JPEG compression is still the mainstream technology in fact. At the same time, due to the rapid development and wide application of FPGA, its rich resource advantages and its powerful parallel advantages are more and more popular. In many applications which require high speed and real-time, researchers tend to use FPGA to achieve image compression. In view of the application of JPEG compression in various fields, most of them are gray images. Therefore, the JPEG compressor realized in this paper is designed for grayscale image. Firstly, this paper introduces the research background and significance of image compression and the current development of JPEG compression. Then the design scheme of JPEG encoder in FPGA is given, and the flow of the basic JPEG compression system used in this design is introduced in detail. Secondly. A new implementation method of DCT transform and quantization, which is an important algorithm in JPEG compression, is also presented. Then the design and implementation of each module in FPGA are introduced one by one according to the idea of modularization. Finally, the test verification of each module is given. This design adopts the Cyclone III series chip of Altera company. In the development environment of QuartusII 13.0, the design is completed. For the two-dimensional DCT transform module, Chen's algorithm is used to make full use of the parallelism of FPGA and multiplier resources. A fast and stable DCT transformation is realized. The quantization module innovates to select 9 different quantization tables in FPGA. The entropy encoding of DC/AC coefficient is realized by lookup table, and the function of each module is tested successively. The image source data is made into MIF file and decoded by the third party software. The test results show that the JPEG encoder achieves the desired function and achieves the design goal.
【學位授予單位】：中北大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TP391.41

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