調(diào)度和優(yōu)化大數(shù)據(jù)計算框架基于CPU/GPU集群
發(fā)布時間：2024-01-29 20:42
本文將討論大數(shù)據(jù)處理。大數(shù)據(jù)作為一種揭示數(shù)據(jù)背后諸如趨勢、性質(zhì)等信息的重要技術,已經(jīng)引起了人們相當大程度的關注。最近,很多研究人員用不同方式提供了大數(shù)據(jù)處理的解決方案。MapReduce是其中一種最流行的類似數(shù)據(jù)處理框架。不管怎樣,一些高端應用,尤其一些科學分析能同時具有大數(shù)據(jù)和云計算特點。因此,我們設計并實施了一個高效的大數(shù)據(jù)處理框架稱為Lit,Lit能夠最大限度發(fā)揮Hadoop和GPUs的力量。本文呈現(xiàn)了Lit的基本設計和結(jié)構(gòu)。更重要的是,我們致力于最大限度地實現(xiàn)CPU和GPU的通信優(yōu)化,并展示數(shù)據(jù)傳送的策略。我方法的靈感一部分來自于科學計算界的代碼最優(yōu)化,并提出了指令合并。指令合并融合了兩個GPU指令的代碼體,目的是1)消除相關指令的無效操作;2)減少GPU指令和GPU存儲之間的數(shù)據(jù)傳輸;3)減少GPU存儲和CPU存儲之間的數(shù)據(jù)傳輸;4)利用存儲器參量的空間和時間位置。此外,我們還介紹了數(shù)據(jù)流優(yōu)化方法以減少不必要的數(shù)據(jù)復制。最后,本文介紹了數(shù)據(jù)通信調(diào)度器,該方法能夠最大限度地減少多余數(shù)據(jù)的傳輸。
【文章頁數(shù)】：75 頁
【學位級別】：碩士
【文章目錄】：
摘要
ABSTRACT
CHAPTER 1: INTRODUCTION
1.1 Thesis background and significance
1.2 Accelerating compute boards: from ASICs to GPU computing
1.3 Computing with Graphic Processing Units
1.3.1 Fixed-function pipelines to fully programmable shaders
1.3.2 General Purpose GPUs
1.3.3 From GPGPU to GPU Computing
1.4 Programming Environments
1.4.1 Low-level Vendor Toolkits
1.4.2 Era of libraries
1.5 Future Trends
1.6 Thesis Objectives
1.7 Thesis organization
CHAPTER 2: LIT: DESIGN HIGH PERFORMANCE MASSIVE DATA COMPUTINGFRAMEWORK BASED ON CPU/GPU CLUSTE
2.1 LIT definition
2.2 Preliminaries and Related work
2.2.1 Data-intensive Computing with Hadoop Map Reduce
2.2.2 GPGPU
2.2.3 GPU based Map Reduce frameworks
2.3 System Design and implementation
2.3.1 Architecture Overview
2.3.2 Lit Workflow
2.3.3 Directives Design
CHAPTER 3: SCHEDULING AND OPTIMIZATION
3.1 Work?ow Optimization
3.2 Memory Copy Optimization
3.3 Instructions fusion Optimization
3.3.1 Instruction Fusion as an Optimization Method
3.3.2 The Benefits of Instruction Fusion
3.3.3 Automating instruction based data Fusion
3.3.4 Instructions Fusion
3.4 CPU/GPU data communication scheduling
3.4.1 Data communication scheduler
CHAPTER 4: RESULTS AND DISCUSSION
4.1 Experimental Setup
4.2 Benchmark et Evaluation
4.3 Evaluation Data set
4.3.1 Measurements with MM, FFT&SCAN
4.3.2 Measurements With instructions Fusion
4.4 Discussion
CONCLUSION
REFERENCES
ACKNOWLEDGEMENT
本文編號：3888809
【文章頁數(shù)】：75 頁
【學位級別】：碩士
【文章目錄】：
摘要
ABSTRACT
CHAPTER 1: INTRODUCTION
1.1 Thesis background and significance
1.2 Accelerating compute boards: from ASICs to GPU computing
1.3 Computing with Graphic Processing Units
1.3.1 Fixed-function pipelines to fully programmable shaders
1.3.2 General Purpose GPUs
1.3.3 From GPGPU to GPU Computing
1.4 Programming Environments
1.4.1 Low-level Vendor Toolkits
1.4.2 Era of libraries
1.5 Future Trends
1.6 Thesis Objectives
1.7 Thesis organization
CHAPTER 2: LIT: DESIGN HIGH PERFORMANCE MASSIVE DATA COMPUTINGFRAMEWORK BASED ON CPU/GPU CLUSTE
2.1 LIT definition
2.2 Preliminaries and Related work
2.2.1 Data-intensive Computing with Hadoop Map Reduce
2.2.2 GPGPU
2.2.3 GPU based Map Reduce frameworks
2.3 System Design and implementation
2.3.1 Architecture Overview
2.3.2 Lit Workflow
2.3.3 Directives Design
CHAPTER 3: SCHEDULING AND OPTIMIZATION
3.1 Work?ow Optimization
3.2 Memory Copy Optimization
3.3 Instructions fusion Optimization
3.3.1 Instruction Fusion as an Optimization Method
3.3.2 The Benefits of Instruction Fusion
3.3.3 Automating instruction based data Fusion
3.3.4 Instructions Fusion
3.4 CPU/GPU data communication scheduling
3.4.1 Data communication scheduler
CHAPTER 4: RESULTS AND DISCUSSION
4.1 Experimental Setup
4.2 Benchmark et Evaluation
4.3 Evaluation Data set
4.3.1 Measurements with MM, FFT&SCAN
4.3.2 Measurements With instructions Fusion
4.4 Discussion
CONCLUSION
REFERENCES
ACKNOWLEDGEMENT
本文編號：3888809
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