OpenRISC處理器寄存器級仿真與實現(xiàn)
發(fā)布時間：2019-06-19 06:21
【摘要】：片上系統(tǒng)（SoC）功能的不斷增強，設(shè)計復(fù)雜度和難度的不斷增加以及產(chǎn)品上市周期的日益縮短，使得處理器仿真技術(shù)得到了越來越多的重視。處理器仿真不僅在硬件設(shè)計階段可作為處理器功能驗證的參照模型發(fā)揮重大作用，而且在軟件設(shè)計階段可作為軟件開發(fā)環(huán)境中的系統(tǒng)支撐平臺而具有重大意義。為了推動開源OpenRISC處理器技術(shù)的發(fā)展，驗證基于SystemC仿真語言進行處理器仿真的優(yōu)點，本文使用SystemC對開源OpenRISC處理器進行了仿真，給出了OpenRISC處理器最小系統(tǒng)的仿真實現(xiàn)，并重點介紹了OpenRISC流水線仿真設(shè)計與實現(xiàn)，可為基于SystemC的OpenRISC處理器的進一步仿真和開發(fā)奠定基礎(chǔ)。 本文的研究工作主要包括： 首先對處理器仿真技術(shù)和SystemC硬件仿真平臺進行了分析；詳細介紹了處理器仿真技術(shù)中的指令集仿真技術(shù)和結(jié)構(gòu)仿真技術(shù)的功能特點，SystenC硬件仿真平臺下的設(shè)計方法學(xué)、仿真內(nèi)核和進程的特點和功能。 其次，分析了OpenRISC1200處理器核的結(jié)構(gòu)框架，并通過對額外單元的裁剪給出了最小系統(tǒng)；最小系統(tǒng)包括整數(shù)流水單元、寄存器單元和內(nèi)存；分析了流水線各級的作用，各級中可能發(fā)生的冒險，發(fā)生冒險的條件以及各種冒險的解決方案。介紹了OpenRISC為匹配主存與CPU性能差異采用的Cache技術(shù)的特點；還對OpenRISC指令集的特點分析和分類。 然后，采用SystemC對OpenRISC處理器流水線進行了仿真設(shè)計，給出了OpenRISC處理器整體設(shè)計框架；實現(xiàn)了流水線中IF級的genpc模塊的仿真，ID級的control模塊和rf模塊的仿真，，EXE級的operandmuxes模塊和alu模塊的仿真，MA級的lsu模塊的仿真和WB級中的wbmux模塊的仿真；同時給出了Cache的仿真實現(xiàn)。 最后結(jié)合SystemC仿真開發(fā)平臺，對其進行必要的初始化工作后；針對數(shù)據(jù)冒險、流水線阻塞、流水線綜合性能和Cache功能分別設(shè)計了相應(yīng)的測試用例，給出了其中相關(guān)的代碼及執(zhí)行結(jié)果；理論分析和實驗結(jié)果都表明基于仿真語言SystemC對OpenRISC處理器核的仿真是可行的，可在此基礎(chǔ)上繼續(xù)開發(fā)和完善并將其用于支持基于OpenRISC的軟硬件系統(tǒng)的開發(fā)設(shè)計。
[Abstract]:With the increasing function of on-chip system (SoC), the increasing complexity and difficulty of design and the shortening of product marketing cycle, more and more attention has been paid to processor simulation technology. Processor simulation can not only play an important role in the hardware design phase as a reference model for processor function verification, but also play an important role in the software design phase as a system support platform in the software development environment. In order to promote the development of open source OpenRISC processor technology and verify the advantages of processor simulation based on SystemC simulation language, this paper uses SystemC to simulate open source OpenRISC processor, gives the simulation implementation of OpenRISC processor minimum system, and focuses on the design and implementation of OpenRISC pipeline simulation, which can lay a foundation for the further simulation and development of OpenRISC processor based on SystemC. The research work of this paper mainly includes: firstly, the processor simulation technology and SystemC hardware simulation platform are analyzed, and the functional characteristics of instruction set simulation technology and structure simulation technology in processor simulation technology, the design methodology under SystenC hardware simulation platform, the characteristics and functions of simulation kernel and process are introduced in detail. Secondly, the structure framework of OpenRISC1200 processor core is analyzed, and the minimum system is given by cutting the additional units. The minimum system includes integer pipeline unit, register unit and memory. The function of pipeline level, the possible risks in all levels, the conditions for taking risks and the solutions of various adventures are analyzed. This paper introduces the characteristics of Cache technology used in OpenRISC to match the performance difference between main memory and CPU, and analyzes and classifies the characteristics of OpenRISC instruction set. Then, the OpenRISC processor pipeline is simulated by SystemC, and the overall design framework of OpenRISC processor is given, including the simulation of IF module in IF level, the simulation of control module and rf module in ID level, the simulation of operandmuxes module and alu module in EXE level, the simulation of lsu module in MA level and the simulation of wbmux module in WB level. At the same time, the simulation implementation of Cache is given. Finally, combined with SystemC simulation development platform, the necessary initialization work is carried out, and the corresponding test cases are designed for data adventure, pipeline blocking, pipeline synthesis performance and Cache function, and the related code and execution results are given. The theoretical analysis and experimental results show that the simulation of OpenRISC processor core based on simulation language SystemC is feasible, on the basis of which it can be further developed and improved and used to support the development and design of software and hardware system based on OpenRISC.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332
本文編號：2502166
[Abstract]:With the increasing function of on-chip system (SoC), the increasing complexity and difficulty of design and the shortening of product marketing cycle, more and more attention has been paid to processor simulation technology. Processor simulation can not only play an important role in the hardware design phase as a reference model for processor function verification, but also play an important role in the software design phase as a system support platform in the software development environment. In order to promote the development of open source OpenRISC processor technology and verify the advantages of processor simulation based on SystemC simulation language, this paper uses SystemC to simulate open source OpenRISC processor, gives the simulation implementation of OpenRISC processor minimum system, and focuses on the design and implementation of OpenRISC pipeline simulation, which can lay a foundation for the further simulation and development of OpenRISC processor based on SystemC. The research work of this paper mainly includes: firstly, the processor simulation technology and SystemC hardware simulation platform are analyzed, and the functional characteristics of instruction set simulation technology and structure simulation technology in processor simulation technology, the design methodology under SystenC hardware simulation platform, the characteristics and functions of simulation kernel and process are introduced in detail. Secondly, the structure framework of OpenRISC1200 processor core is analyzed, and the minimum system is given by cutting the additional units. The minimum system includes integer pipeline unit, register unit and memory. The function of pipeline level, the possible risks in all levels, the conditions for taking risks and the solutions of various adventures are analyzed. This paper introduces the characteristics of Cache technology used in OpenRISC to match the performance difference between main memory and CPU, and analyzes and classifies the characteristics of OpenRISC instruction set. Then, the OpenRISC processor pipeline is simulated by SystemC, and the overall design framework of OpenRISC processor is given, including the simulation of IF module in IF level, the simulation of control module and rf module in ID level, the simulation of operandmuxes module and alu module in EXE level, the simulation of lsu module in MA level and the simulation of wbmux module in WB level. At the same time, the simulation implementation of Cache is given. Finally, combined with SystemC simulation development platform, the necessary initialization work is carried out, and the corresponding test cases are designed for data adventure, pipeline blocking, pipeline synthesis performance and Cache function, and the related code and execution results are given. The theoretical analysis and experimental results show that the simulation of OpenRISC processor core based on simulation language SystemC is feasible, on the basis of which it can be further developed and improved and used to support the development and design of software and hardware system based on OpenRISC.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332
【參考文獻】
相關(guān)期刊論文 前1條
1 楊榮;朱建彬;胡博;朱勇;;基于SystemC的片上系統(tǒng)設(shè)計[J];武漢科技學(xué)院學(xué)報;2008年07期
本文編號：2502166
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