基于VPX標(biāo)準(zhǔn)和多核DSP陣列的信息處理平臺(tái)設(shè)計(jì)
[Abstract]:With the increasing demand of high performance integrated information processing system for operation processing speed, bus bandwidth, data processing and working environment, the traditional embedded information processing platform can not meet the actual needs of technology development and product development. The information processing platform based on VPX (VITA46) standard and multi-core DSP array has strong data processing ability, communication ability and high performance network switching ability. Its highest theoretical bandwidth is 40GB / s, and it has good universality and expansibility. It is the development trend and direction of the new generation of high performance integrated information processing platform. Aiming at the requirement of high-speed real-time information processing, this paper designs an information processing platform based on VPX standard and multi-core DSP array to realize high-speed data transmission ability and strong information processing ability. The information processing platform adopts DSP parallel processing structure based on VPX switching standard, Serial RapidIO switching technology is used to solve the communication of large amount of data between processors, and multi-core DSP parallel processing is used to realize strong information processing ability. Multi-channel high-speed optical fiber communication bus is used to realize the external communication ability of high bandwidth. According to the overall requirements and overall design scheme of the information processing platform, this paper realizes the system composition, hardware resource planning and the design scheme of each functional module of the information processing platform. The hardware design of Serial RapidIO switching module board and TMS320C6678DSP array processing module board is realized. The realized information processing platform is applied to two information processing systems with different scales and uses. The test results show that the platform has strong practicability and convenient scalability / reduction performance.
【學(xué)位授予單位】:天津大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2012
【分類號(hào)】:TP274;TP368.12
【參考文獻(xiàn)】
相關(guān)期刊論文 前10條
1 楊光燦;黃鈺林;楊建宇;;基于VPX標(biāo)準(zhǔn)的SAR實(shí)時(shí)信號(hào)處理板設(shè)計(jì)[J];電訊技術(shù);2009年12期
2 魏鵬;羅武勝;杜列波;;PCI Express總線及其應(yīng)用設(shè)計(jì)研究[J];電測與儀表;2007年02期
3 謝民 ,高梅國 ,劉國滿;DSP互連技術(shù)的發(fā)展[J];電子產(chǎn)品世界;2004年Z1期
4 王勇;張平;;高性能多DSP互連技術(shù)[J];電子產(chǎn)品世界;2009年04期
5 張?zhí)炝?張思敏;;CPCI-E與VPX總線標(biāo)準(zhǔn)的比較分析[J];工業(yè)控制計(jì)算機(jī);2009年07期
6 ;IDT推出針對嵌入式市場的高性能、低功耗串行RapidIO交換器[J];電子與電腦;2007年12期
7 谷國太;肖漢;;并行計(jì)算與并行處理技術(shù)的應(yīng)用研究[J];河南理工大學(xué)學(xué)報(bào)(自然科學(xué)版);2009年05期
8 屈磊;宋慰軍;茍冬榮;柴小麗;奚軍;;基于SRIO的多DSP并行信號(hào)處理系統(tǒng)[J];計(jì)算機(jī)工程;2008年S1期
9 姬葉華;;基于VPX總線的抗惡劣環(huán)境計(jì)算機(jī)[J];計(jì)算機(jī)工程;2008年S1期
10 周博;王石記;邱衛(wèi)東;彭澄廉;;SHUM-UCOS:基于統(tǒng)一多任務(wù)模型可重構(gòu)系統(tǒng)的實(shí)時(shí)操作系統(tǒng)[J];計(jì)算機(jī)學(xué)報(bào);2006年02期
相關(guān)碩士學(xué)位論文 前1條
1 汪星宇;RapidIO技術(shù)在信號(hào)處理系統(tǒng)中的應(yīng)用與研究[D];南京理工大學(xué);2009年
本文編號(hào):2495093
本文鏈接:http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2495093.html