【摘要】：隨著集成電路和航天事業(yè)的發(fā)展,片上系統(tǒng)(So C)芯片越來(lái)越多地被應(yīng)用在輻射環(huán)境中。存儲(chǔ)器是So C中的重要組成部分,對(duì)存儲(chǔ)器進(jìn)行抗輻射加固是當(dāng)今存儲(chǔ)器的一個(gè)重點(diǎn)研究方向。本文采用SMIC0.18μm工藝設(shè)計(jì)了一個(gè)應(yīng)用于抗輻射So C中的加固SRAM存儲(chǔ)器。本文首先分析了單粒子翻轉(zhuǎn)效應(yīng)、單粒子閂鎖效應(yīng)和總劑量效應(yīng),以及常用的加固方法,并針對(duì)這三種輻射效應(yīng)確定了本設(shè)計(jì)中使用的加固方法。隨后根據(jù)設(shè)計(jì)要求進(jìn)行8Kb存儲(chǔ)器的架構(gòu)設(shè)計(jì)和時(shí)序設(shè)計(jì)。針對(duì)單粒子翻轉(zhuǎn)進(jìn)行存儲(chǔ)單元的電路級(jí)加固,采用12管DICE電路結(jié)構(gòu)設(shè)計(jì)了存儲(chǔ)器陣列。然后對(duì)存儲(chǔ)器的外圍電路進(jìn)行設(shè)計(jì)和功能仿真,包括行列譯碼電路、數(shù)據(jù)輸入/輸出電路、靈敏放大器和時(shí)鐘電路。并著重對(duì)鎖存器型靈敏放大器的結(jié)構(gòu)、功能和性能進(jìn)行分析。完成了完整的存儲(chǔ)器的設(shè)計(jì)與仿真,本設(shè)計(jì)中的SRAM存儲(chǔ)器工作頻率可以達(dá)到100MHz。訪問(wèn)時(shí)間約為0.926ns,功耗為3.88m W。最后進(jìn)行版圖設(shè)計(jì),在版圖中使用電源接觸和襯底接觸對(duì)單粒子閂鎖效應(yīng)和總劑量效應(yīng)進(jìn)行加固,存儲(chǔ)器版圖大小為603900.3432μm2。對(duì)版圖進(jìn)行了寄生參數(shù)提取并進(jìn)行了后仿真,后仿結(jié)果表明存儲(chǔ)器功能正確。訪問(wèn)時(shí)間為1.21ns,功耗為5.136m W,與前仿結(jié)果相差不大。
[Abstract]:With the development of integrated circuit and space industry, on-chip system (So C) chip is more and more used in radiation environment. Memory is an important part of So C. radiation hardening of memory is a key research direction of memory today. In this paper, a hardened SRAM memory used in radiation resistant So C is designed by using SMIC 0.18 渭 m process. In this paper, the single-particle flip-over effect, the single-particle latch-up effect and the total dose effect, as well as the commonly used reinforcement methods are analyzed, and the strengthening methods used in this design are determined according to these three radiation effects. Then according to the design requirements, the architecture design and timing design of 8Kb memory are carried out. A memory array based on 12-transistor DICE circuit structure is designed for the circuit-level reinforcement of single-particle flip-over memory cells. Then the peripheral circuit of memory is designed and simulated, including column decoding circuit, data input / output circuit, sensitive amplifier and clock circuit. The structure, function and performance of the lock-in sensitive amplifier are analyzed. The complete memory design and simulation are completed. The working frequency of SRAM memory in this design can reach 100 MHz. The access time is about 0.926 nsand the power consumption is 3.88m W. Finally, the layout design is carried out. The single-particle latch-up effect and total dose effect are strengthened by using power contact and substrate contact in the layout. The size of the memory layout is 603900.3432um2. The parasitic parameters of the layout are extracted and the post-simulation results show that the memory function is correct. The access time is 1.21 ns and the power consumption is 5.136 MW, which is not much different from the previous simulation results.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP333

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