字線脈沖控制解決異步雙端口SRAM中的寫(xiě)干擾
發(fā)布時(shí)間：2019-03-26 14:09
【摘要】：為了避免雙端口SRAM中由寫(xiě)干擾造成的數(shù)據(jù)寫(xiě)入困難,利用寫(xiě)干擾的時(shí)鐘偏移相關(guān)性提出了一種新的字線脈沖控制技術(shù),確定了寫(xiě)干擾下成功寫(xiě)入數(shù)據(jù)所需的最小寫(xiě)字線脈寬,并設(shè)計(jì)了時(shí)鐘沿檢測(cè)電路來(lái)解決寫(xiě)操作造成的寫(xiě)干擾.采用TSN28HPM工藝,抽取RC寄生參數(shù)后進(jìn)行了后端仿真,結(jié)果表明所提方案可行有效.
[Abstract]:In order to avoid the data writing difficulty caused by write interference in dual-port SRAM, a new word line pulse control technique is proposed by using the clock offset correlation of write interference, and the minimum writing line pulse width required for successful write data under write interference is determined. And the clock edge detection circuit is designed to solve the write interference caused by write operation. The TSN28HPM process is used to extract the parasitic parameters of RC and the back-end simulation is carried out. The results show that the proposed scheme is feasible and effective.
【作者單位】： 上海交通大學(xué)微電子學(xué)院;
【分類號(hào)】：TP333
本文編號(hào)：2447625
[Abstract]:In order to avoid the data writing difficulty caused by write interference in dual-port SRAM, a new word line pulse control technique is proposed by using the clock offset correlation of write interference, and the minimum writing line pulse width required for successful write data under write interference is determined. And the clock edge detection circuit is designed to solve the write interference caused by write operation. The TSN28HPM process is used to extract the parasitic parameters of RC and the back-end simulation is carried out. The results show that the proposed scheme is feasible and effective.
【作者單位】： 上海交通大學(xué)微電子學(xué)院;
【分類號(hào)】：TP333
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1 D.J.Kimniment ,唐天杰;集成聯(lián)想存貯器系統(tǒng)[J];電子計(jì)算機(jī)參考資料;1977年12期
2 張?jiān)?;256KbCMOS模擬SRAM[J];電子技術(shù);1987年10期
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