【摘要】：為了避免雙端口SRAM中由寫干擾造成的數(shù)據(jù)寫入困難,利用寫干擾的時鐘偏移相關(guān)性提出了一種新的字線脈沖控制技術(shù),確定了寫干擾下成功寫入數(shù)據(jù)所需的最小寫字線脈寬,并設(shè)計了時鐘沿檢測電路來解決寫操作造成的寫干擾.采用TSN28HPM工藝,抽取RC寄生參數(shù)后進行了后端仿真,結(jié)果表明所提方案可行有效.
[Abstract]:In order to avoid the data writing difficulty caused by write interference in dual-port SRAM, a new word line pulse control technique is proposed by using the clock offset correlation of write interference, and the minimum writing line pulse width required for successful write data under write interference is determined. And the clock edge detection circuit is designed to solve the write interference caused by write operation. The TSN28HPM process is used to extract the parasitic parameters of RC and the back-end simulation is carried out. The results show that the proposed scheme is feasible and effective.
【作者單位】： 上海交通大學微電子學院;
【分類號】：TP333

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