一種OTP存儲(chǔ)器讀出系統(tǒng)的設(shè)計(jì)技術(shù)研究
發(fā)布時(shí)間：2018-12-14 23:22
【摘要】：OTP存儲(chǔ)器是一種一次可編程的只讀存儲(chǔ)器,具有可靠性高、穩(wěn)定性高、保密性強(qiáng)、存儲(chǔ)單元面積小等特點(diǎn)。因此OTP存儲(chǔ)器在保密性要求高、穩(wěn)定性要求高、只需一次編程等場合,應(yīng)用非常廣泛。例如應(yīng)用在RFID、密鑰存儲(chǔ)芯片、以及衛(wèi)星、火箭、航天飛機(jī)、太空飛船、國際空間站等環(huán)境復(fù)雜,干擾強(qiáng)的地方。這方面的器件在我國幾乎完全依賴進(jìn)口,但是發(fā)達(dá)國家對(duì)相關(guān)技術(shù)和產(chǎn)品對(duì)我實(shí)施禁運(yùn)禁售,限制了我國軍事、工業(yè)等領(lǐng)域的發(fā)展。所以對(duì)這方面集成電路的研究有助于我國集成電路的發(fā)展。 本文的目的是設(shè)計(jì)一款適用于OTP存儲(chǔ)器的讀出系統(tǒng),包括與讀取操作相關(guān)的所有電路和模塊,如譯碼器、控制電路、靈敏放大器、鎖存電路、雙向數(shù)據(jù)端口等模塊。文章的前兩章介紹了OTP存儲(chǔ)器的國內(nèi)外研究現(xiàn)狀,OTP存儲(chǔ)器的結(jié)構(gòu)以及OTP單元用作存儲(chǔ)單元的原理；然后第三章詳細(xì)闡述了OTP存儲(chǔ)器讀出系統(tǒng)的設(shè)計(jì)和仿真,包括譯碼器、地址檢測電路、控制信號(hào)產(chǎn)生電路、靈敏放大器、兩級(jí)鎖存電路、雙向數(shù)據(jù)端口等子模塊的電路設(shè)計(jì)及仿真結(jié)果；接下來第四章詳細(xì)介紹了芯片的版圖設(shè)計(jì)、寄生參數(shù)提取,并用FineSim對(duì)芯片進(jìn)行了版圖后仿真.最后,介紹了芯片的測試平臺(tái)、測試方法以及測試過程,并對(duì)芯片讀出系統(tǒng)的功能和速度進(jìn)行了測試,測試結(jié)果表明讀出系統(tǒng)工作正常,達(dá)到了電路的設(shè)計(jì)指標(biāo)。 本文所設(shè)計(jì)的OTP存儲(chǔ)器讀出系統(tǒng)具有一定的通用性和可移植性,應(yīng)用廣泛。雖基于16Kbit OTP存儲(chǔ)器,但并不局限于此,同樣可以用在512Kbit、1Mbit甚至容量更大的OTP存儲(chǔ)器芯片中,需要改變的只是小部分電路,整個(gè)讀出系統(tǒng)可以很容易的嵌入進(jìn)去,實(shí)現(xiàn)穩(wěn)定準(zhǔn)確的讀取操作。
[Abstract]:OTP memory is a kind of single programmable read-only memory, which has the characteristics of high reliability, high stability, strong confidentiality and small storage cell area. Therefore, OTP memory is widely used in many applications, such as high security, high stability and only one programming. For example, applications in RFID, key storage chips, as well as satellites, rockets, space shuttles, spaceships, international space stations and other complex environments, strong interference. The devices in this field almost rely on imports in China, but the developed countries have imposed embargo on the related technology and products, which has restricted the development of military, industrial and other fields in our country. So the research of integrated circuit in this field is helpful to the development of integrated circuit in our country. The purpose of this paper is to design a readout system suitable for OTP memory, including all circuits and modules related to read operation, such as decoder, control circuit, sensitive amplifier, latch circuit, bidirectional data port and so on. The first two chapters of this paper introduce the research status of OTP memory at home and abroad, the structure of OTP memory and the principle of OTP unit as memory cell. Then the third chapter describes the design and simulation of OTP memory readout system, including decoder, address detection circuit, control signal generation circuit, sensitive amplifier, two-stage latch circuit. The circuit design and simulation results of the bidirectional data port isobaric module; In the fourth chapter, the layout design and parasitic parameter extraction of the chip are introduced in detail, and the post-layout simulation of the chip is carried out with FineSim. Finally, the test platform, test method and test process of the chip are introduced. The function and speed of the chip readout system are tested. The test results show that the readout system works normally and achieves the design target of the circuit. The OTP memory readout system designed in this paper has certain generality and portability, and is widely used. Although it is based on 16Kbit OTP memory, but it is not limited to this, it can also be used in 512kbit bit 1Mbit or larger OTP memory chip. Only a small part of the circuit needs to be changed, so the whole readout system can be easily embedded. To achieve stable and accurate read operation.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333
本文編號(hào)：2379492
[Abstract]:OTP memory is a kind of single programmable read-only memory, which has the characteristics of high reliability, high stability, strong confidentiality and small storage cell area. Therefore, OTP memory is widely used in many applications, such as high security, high stability and only one programming. For example, applications in RFID, key storage chips, as well as satellites, rockets, space shuttles, spaceships, international space stations and other complex environments, strong interference. The devices in this field almost rely on imports in China, but the developed countries have imposed embargo on the related technology and products, which has restricted the development of military, industrial and other fields in our country. So the research of integrated circuit in this field is helpful to the development of integrated circuit in our country. The purpose of this paper is to design a readout system suitable for OTP memory, including all circuits and modules related to read operation, such as decoder, control circuit, sensitive amplifier, latch circuit, bidirectional data port and so on. The first two chapters of this paper introduce the research status of OTP memory at home and abroad, the structure of OTP memory and the principle of OTP unit as memory cell. Then the third chapter describes the design and simulation of OTP memory readout system, including decoder, address detection circuit, control signal generation circuit, sensitive amplifier, two-stage latch circuit. The circuit design and simulation results of the bidirectional data port isobaric module; In the fourth chapter, the layout design and parasitic parameter extraction of the chip are introduced in detail, and the post-layout simulation of the chip is carried out with FineSim. Finally, the test platform, test method and test process of the chip are introduced. The function and speed of the chip readout system are tested. The test results show that the readout system works normally and achieves the design target of the circuit. The OTP memory readout system designed in this paper has certain generality and portability, and is widely used. Although it is based on 16Kbit OTP memory, but it is not limited to this, it can also be used in 512kbit bit 1Mbit or larger OTP memory chip. Only a small part of the circuit needs to be changed, so the whole readout system can be easily embedded. To achieve stable and accurate read operation.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333
【參考文獻(xiàn)】
相關(guān)期刊論文 前6條
1 孫承松;張麗娟;李新;;ONO反熔絲的研究[J];沈陽工業(yè)大學(xué)學(xué)報(bào);2006年05期
2 潘培勇;趙琳娜;王春早;薛忠杰;;一種新型地址變化探測技術(shù)在SRAM中的應(yīng)用[J];微計(jì)算機(jī)信息;2007年05期
3 李玉紅;趙元富;岳素格;梁國朕;林任;;0.18μm工藝下單粒子加固鎖存器的設(shè)計(jì)與仿真[J];微電子學(xué)與計(jì)算機(jī);2007年12期
4 李侃;伍冬;王雪強(qiáng);譙鳳英;鄧寧;潘立陽;;基于SOI-SONOS存儲(chǔ)器的高速輻照加固靈敏放大器設(shè)計(jì)[J];微電子學(xué)與計(jì)算機(jī);2010年05期
5 袁蕊林;陳奕含;羅前;李曼;李平;;一種OTP存儲(chǔ)器高速讀出機(jī)制的設(shè)計(jì)[J];微電子學(xué)與計(jì)算機(jī);2012年01期
6 袁蕊林;陳志鈞;張頡夫;陳奕含;;一種OTP存儲(chǔ)器片上時(shí)序信號(hào)產(chǎn)生電路的設(shè)計(jì)[J];電子元器件應(yīng)用;2011年12期
，本文編號(hào)：2379492
本文鏈接：http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2379492.html
最近更新
教材專著
