【摘要】：針對傳統(tǒng)的混合基算法在實(shí)現(xiàn)余數(shù)系統(tǒng)到二進(jìn)制系統(tǒng)轉(zhuǎn)換過程中的并行性問題,應(yīng)用改進(jìn)的混合基算法,研究與設(shè)計(jì)了一個(gè)基于模集合{2n,2n-1,2n+1-1,2n-1-1}的后置轉(zhuǎn)換電路.模2n-1形式的模加法器采用相對簡單的實(shí)現(xiàn)結(jié)構(gòu),使設(shè)計(jì)的電路避免了只讀存儲(chǔ)器及時(shí)序電路的引入,整個(gè)后置轉(zhuǎn)換電路完全由簡單組合邏輯及加法器級聯(lián)實(shí)現(xiàn),縮短了關(guān)鍵路徑延時(shí),減小了功率消耗,與已有的相同動(dòng)態(tài)范圍余數(shù)系統(tǒng)后置轉(zhuǎn)換電路相比,性能優(yōu)勢明顯.
[Abstract]:Aiming at the parallelism of the traditional hybrid basis algorithm in the process of realizing the conversion of residue system to binary system, a post-conversion circuit based on the modular set {2nn2n-1n-1 + 2n 1-1n + 2n-1-1} is studied and designed by using the improved hybrid basis algorithm. The modular adder in the form of modular 2n-1 adopts a relatively simple implementation structure, which avoids the introduction of read-only memory and sequential circuits, and the whole post-conversion circuit is completely realized by simple combinatorial logic and adder cascading. The critical path delay is shortened and the power consumption is reduced. Compared with the existing post-conversion circuit in the same dynamic range, the performance of the system has obvious advantages.
【作者單位】： 華南理工大學(xué)電子與信息學(xué)院;
【基金】：國家自然科學(xué)基金項(xiàng)目(61274085) 華南理工大學(xué)中央高�；究蒲袑W(xué)生項(xiàng)目(10561201435)
【分類號】：O156;TP332.2

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本文編號：2279769