【摘要】：本文針對(duì)片上多核網(wǎng)絡(luò)處理器的結(jié)構(gòu)對(duì)多核共享存儲(chǔ)控制系統(tǒng)進(jìn)行了設(shè)計(jì)與優(yōu)化。主要設(shè)計(jì)完成了共享存儲(chǔ)控制器片上接口隊(duì)列結(jié)構(gòu)、基于優(yōu)先級(jí)的存儲(chǔ)訪問指令仲裁模塊、多處理器與存儲(chǔ)器進(jìn)行數(shù)據(jù)交互的推拉引擎結(jié)構(gòu)、存儲(chǔ)控制器接口等核心模塊功能。重點(diǎn)研究了共享存儲(chǔ)控制器與多線程包處理引擎之間的異步訪存方式、片上包緩沖結(jié)構(gòu)RFIFO和TFIFO與存儲(chǔ)控制器之間實(shí)現(xiàn)數(shù)據(jù)直接轉(zhuǎn)發(fā)的DMA通道。 考慮到對(duì)存儲(chǔ)器長(zhǎng)時(shí)間的訪存延時(shí)，本文結(jié)合片上多核網(wǎng)絡(luò)處理器對(duì)片外存儲(chǔ)器充當(dāng)轉(zhuǎn)發(fā)表和數(shù)據(jù)包緩沖的需求，對(duì)共享存儲(chǔ)控制器的結(jié)構(gòu)進(jìn)行了優(yōu)化和改進(jìn)，通過增加指令預(yù)取電路和對(duì)存儲(chǔ)控制接口的改進(jìn)可實(shí)現(xiàn)對(duì)SDRAM存儲(chǔ)器的動(dòng)態(tài)優(yōu)化，根據(jù)連續(xù)指令地址信息動(dòng)態(tài)選擇同行同bank優(yōu)化或bank交錯(cuò)優(yōu)化方案，最大限度利用了可以優(yōu)化的指令。 最后并將共享存儲(chǔ)控制系統(tǒng)的RTL級(jí)電路在XDNP多核網(wǎng)絡(luò)處理器驗(yàn)證平臺(tái)上進(jìn)行了功能驗(yàn)證，結(jié)果表明控制的各個(gè)功能模塊設(shè)計(jì)正確，能夠完成多核處理器對(duì)片外SDRAM的訪問。性能分析表明指令預(yù)取電路結(jié)構(gòu)支持的動(dòng)態(tài)優(yōu)化方式比靜態(tài)優(yōu)化方式對(duì)存儲(chǔ)器性能提升的效果更大。并且優(yōu)化性能隨著指令數(shù)的增加而增加，在連續(xù)執(zhí)行指令數(shù)大于35以后，由于系統(tǒng)固有發(fā)送微包程序指令的限制系統(tǒng)性能提升效果達(dá)到穩(wěn)定，，系統(tǒng)性能最大可以提升到45%。
[Abstract]:This paper designs and optimizes the multi-core shared storage control system for the multi-core network processor. The main functions of this paper are as follows: interface queue structure of shared memory controller, priority based memory access instruction arbitration module, push-pull engine structure of data interaction between multi-processor and memory, memory controller interface and other core module functions. The asynchronous memory access between the shared storage controller and the multithreaded packet processing engine is studied, and the DMA channel between the on-chip packet buffer structure (RFIFO) and the memory controller (TFIFO) is used to transmit the data directly. Considering the long time delay of memory access, this paper optimizes and improves the structure of shared memory controller by considering the demand of on-chip multi-core network processor to serve as forwarding table and packet buffer for off-chip memory. The dynamic optimization of SDRAM memory can be realized by adding instruction prefetching circuit and improving the memory control interface. According to the continuous instruction address information, we can dynamically select the peer optimization scheme with bank or bank interleaving optimization scheme. Maximize the use of optimizable instructions. Finally, the RTL level circuit of the shared memory control system is verified on the XDNP multi-core network processor verification platform. The results show that each functional module is designed correctly and the multi-core processor can access the off-chip SDRAM. The performance analysis shows that the dynamic optimization method supported by the instruction prefetching circuit structure is more effective than the static optimization mode in improving the memory performance. The optimization performance increases with the increase of the number of instructions. After the number of instructions is more than 35, the system performance can be improved to 45% because of the limitation of the inherent micropacket program instruction to improve the performance of the system.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333;TN47

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