【摘要】：為解決M5-edge模擬器的理想化集總式取指令結(jié)構(gòu)對基于EDGE體系結(jié)構(gòu)設(shè)計空間探索的限制問題,對原模擬器的取指令前段進(jìn)行分布式設(shè)計,包括總體的功能、具體的取指單元及單元間的互連網(wǎng)絡(luò)設(shè)計,并在取指令塊頭的方式上設(shè)計了固定方式和循環(huán)方式兩種方案.通過對實(shí)現(xiàn)后的結(jié)構(gòu)進(jìn)行在不同分布單元數(shù)量條件下的仿真分析,得到從理想集總式取指結(jié)構(gòu)到實(shí)際分布式結(jié)構(gòu)的性能下降關(guān)系和不同取指令塊頭方式的優(yōu)劣.通過進(jìn)一步分析,得出通信延遲和緩存缺失率對處理器性能的影響.
[Abstract]:In order to solve the problem that the idealized lumped instruction structure of M5-edge simulator limits the exploration of design space based on EDGE architecture, the distributed design of the former simulator is carried out, including the overall function. The design of the interconnect network between the reference unit and the unit, and the design of the fixed mode and the cyclic mode in the way of taking the instruction block are also presented in this paper. Through the simulation and analysis of the realized structure under the condition of different number of distributed units, the relationship between the performance degradation of the ideal lumped reference structure and the actual distributed structure and the advantages and disadvantages of different instruction block methods are obtained. Through further analysis, the effect of communication delay and cache missing rate on processor performance is obtained.
【作者單位】： 哈爾濱工業(yè)大學(xué)航天學(xué)院;
【分類號】：TP332
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本文編號：2192050