65nm高性能SRAM體系架構(gòu)及電路實現(xiàn)
發(fā)布時間：2018-08-12 14:17
【摘要】：嵌入式SRAM作為SoC芯片的重要組成部分,其性能決定了高性能SoC整體性能的提升。近年來,雖然得益于集成電路設(shè)計方法,EDA技術(shù)及集成電路制造工藝的發(fā)展,嵌入式SRAM在速度,密度及功耗等性能指標上得到了很大程度的提升,但是微處理器的處理速度的提升高于SRAM性能提升速度,因此LSRAM性能的進一步提高仍然是高性能SoC的迫切需求。 本論文基于國家核高基重大專項《嵌入式CPU SRAM編譯器關(guān)鍵技術(shù)研究》在SMIC65nm藝下實現(xiàn)了一款16Kb高性能SRAM設(shè)計。為滿足在1.2V,典型工藝角,室溫下讀出延時(Tcq)小于800ps,面積小于28826.512um2的設(shè)計指標,本論文從SRAM整體架構(gòu)設(shè)計,高性能譯碼電路設(shè)計,精確時序電路產(chǎn)生,面積優(yōu)化等多方面進行了優(yōu)化設(shè)計 首先,本論文對現(xiàn)有的SRAM架構(gòu)設(shè)計方法的優(yōu)缺點,適用條件做了詳細的分析。在分析的基礎(chǔ)上,根據(jù)本論文中16KbSRAM的特點,選擇存儲陣列劃分的架構(gòu)設(shè)計方法來實現(xiàn)該16KbSRAM。為選擇最優(yōu)的陣列劃分方法,文中對兩種劃分方法進行仿真驗證,比較其性能及實現(xiàn)面積,選擇了其中一種最優(yōu)的SRAM架構(gòu)實現(xiàn)方法；其次,考慮到精確的SRAM時序產(chǎn)生電路設(shè)計能有效的提高SRAM的整體工作速度,降低功耗,本論文對靖確的SRAM時序產(chǎn)生電路進行了詳細而深入的分析。早期采用反相器鏈來實現(xiàn)時序控制的方式存在反相器延時不能有效跟隨存儲單元讀操作放電延時的問題,而且在深亞微米工藝下,工藝偏差增大,這種問題越來越突出。為解決反相器鏈時序產(chǎn)生電路的缺陷,電容比及電流比復(fù)制位線技術(shù)被提出,這兩種復(fù)制位線技術(shù)采用冗余的復(fù)制列及復(fù)制單元來模擬存儲單元的讀操作以產(chǎn)生SRAM控制信號。電容比及電流比復(fù)制位線技術(shù)中復(fù)制列的單元與存儲陣列單元一致,保證復(fù)制列的寄生電容與存儲陣列的位線寄生電容一致,復(fù)制單元讀操作電流與當(dāng)前讀操作單元電流一致,因此能準確的跟隨SRAM讀操作放電延時。上述兩種技術(shù)只能保證在固定電源電壓下時序信號的精確產(chǎn)生,當(dāng)SRAM工作在某一電壓范圍內(nèi)時,采用電容比及電流比技術(shù)實現(xiàn)時序控制時出現(xiàn)隨電源電壓變化,位線放電延時增加,降低了SRAM性能的問題。本論文針對工作在一定電壓范圍內(nèi)的SRAM,創(chuàng)造性的提出一種可編程復(fù)制位線技術(shù)保證SRAM在所有工作電壓下均能精確產(chǎn)生時序信號,仿真與測試結(jié)果均顯示本文中提出的可編程復(fù)制位線技術(shù)很好地提升了SRAM性能；再次,本論文通過對現(xiàn)有譯碼電路結(jié)構(gòu)形式及特點進行了分析比較,選擇全靜態(tài)譯碼邏輯來實現(xiàn)本論文中16Kb SRAM。在對譯碼電路中晶體管進行尺寸設(shè)定時,采用邏輯努力分析方法,確定在65nm工藝下獲得最優(yōu)延時的邏輯門的扇出值�？紤]到65nm工藝下,線延時已經(jīng)能夠與邏輯門延時相比擬,特別是在SRAM中從預(yù)譯碼到二級譯碼需經(jīng)過很長互連線的情況.本論文討論了采用包含互連線延時的邏輯路徑設(shè)計方法,并最終實現(xiàn)了本論文中的高速譯碼電路。 本論文實現(xiàn)的16Kb SRAM在典型電壓下后仿讀出延時為540ps,滿足了設(shè)計指標。在SMIC65nm工藝下的流片測試結(jié)果表明該16Kb SRAM能工作在0.8V-1.4V電源電壓范圍,工作頻率范圍為440MHz-1.62GHz。在1.2V典型電源電壓、室溫條件下,SRAM工作速度達到1.22GHz,面積為22762.76μm2遠小于設(shè)計要求的28826.512um2。為驗證論文中可編程復(fù)制位線技術(shù)的有效性,本論文對采用新技術(shù)及電流比復(fù)制位線技術(shù)實現(xiàn)的SRAM進行比較,結(jié)果表明隨電源電壓變化采用新技術(shù)的SRAM的最高工作頻率比電流比復(fù)制位線技術(shù)提升了4.3%-9.5%。
[Abstract]:Embedded SRAM is an important part of SoC chip, its performance determines the overall performance of high-performance SoC. In recent years, although thanks to the development of integrated circuit design method, EDA technology and integrated circuit manufacturing technology, embedded SRAM has been greatly improved in speed, density and power consumption, but slightly. The processing speed of the processor is faster than that of SRAM, so further improvement of LSRAM performance is still an urgent need of high performance SoC.
In order to meet the requirements of 1.2V, typical process angle, room temperature read-out delay (Tcq) less than 800ps and area less than 28826.512um2, this paper designs a high performance SRAM with SMIC65nm technology. The design of decoding circuit, the generation of precise sequential circuits, and the optimization of the area are optimized.
Firstly, this paper makes a detailed analysis of the advantages and disadvantages of the existing SRAM architecture design methods and the applicable conditions. On the basis of the analysis, according to the characteristics of the 16Kb SRAM in this paper, the architecture design method of memory array partitioning is selected to realize the 16Kb SRAM. To select the optimal array partitioning method, two partitioning methods are simulated in this paper. Verify, compare its performance and implementation area, choose one of the best SRAM architecture implementation method; secondly, considering the accurate design of SRAM sequence generation circuit can effectively improve the overall speed of SRAM and reduce power consumption, this paper makes a detailed and in-depth analysis of Jingqing SRAM sequence generation circuit. There is a problem that the inverter delay can not effectively follow the discharge delay of the storage unit in order to realize the timing control of the inverter chain, and the process deviation is increasing in the deep submicron process, which is becoming more and more prominent. The two replication bit-line technologies use redundant replication columns and replication units to simulate the read operation of the storage unit to generate SRAM control signals. In capacitance ratio and current ratio replication bit-line technology, the units of replication columns are identical with the storage array units, ensuring that the parasitic capacitance of the replication column is identical with the parasitic capacitance of the storage array bit-line, and the replication unit reads. The operating current is the same as the current of the current read-operate unit, so it can accurately follow the SRAM read-operate discharge delay. The above two techniques can only ensure the accurate generation of the timing signal under the fixed power supply voltage. When the SRAM works in a certain voltage range, the capacitance ratio and current ratio technology are used to achieve the timing control when the power supply voltage is changed. In this paper, a programmable duplicate bit-line technology is creatively proposed for SRAM operating in a certain range of voltage to ensure that SRAM can accurately generate timing signals at all operating voltages. The simulation and test results show that the programmable duplicate bit-line proposed in this paper can be used to solve the problem of SRAM performance. The technology improves the performance of SRAM very well. Thirdly, through analyzing and comparing the structure and characteristics of the existing decoding circuit, this paper chooses full-static decoding logic to implement the 16Kb SRAM in this paper. Considering that the line delay can be compared with the gate delay in 65nm process, especially in SRAM where the pre-decoding to the secondary decoding takes a long interconnection, this paper discusses the logical path design method including the interconnection delay, and finally realizes the high-speed decoding in this paper. Code circuit.
The sixteen-kb SRAM realized in this paper has a read-out delay of 540 PS under typical voltage, which meets the design requirements. The results of the chip test under SMIC65nm process show that the sixteen-kb SRAM can operate in the voltage range of 0.8V-1.4V, the frequency range of 440MHz-1.62GHz, the typical power supply voltage of 1.2V, and the SRAM working speed reaches 1.22GH at room temperature. Z, the area is 22762.76 um 2, which is much smaller than 28826.512 um 2. In order to verify the validity of the programmable duplicate bit-line technology, this paper compares the SRAM realized by the new technology and the current-ratio duplicate bit-line technology. The results show that the highest specific frequency and current-ratio duplicate bit of the new technology can be achieved with the change of power supply voltage. Line technology improves 4.3%-9.5%.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333
本文編號：2179310
[Abstract]:Embedded SRAM is an important part of SoC chip, its performance determines the overall performance of high-performance SoC. In recent years, although thanks to the development of integrated circuit design method, EDA technology and integrated circuit manufacturing technology, embedded SRAM has been greatly improved in speed, density and power consumption, but slightly. The processing speed of the processor is faster than that of SRAM, so further improvement of LSRAM performance is still an urgent need of high performance SoC.
In order to meet the requirements of 1.2V, typical process angle, room temperature read-out delay (Tcq) less than 800ps and area less than 28826.512um2, this paper designs a high performance SRAM with SMIC65nm technology. The design of decoding circuit, the generation of precise sequential circuits, and the optimization of the area are optimized.
Firstly, this paper makes a detailed analysis of the advantages and disadvantages of the existing SRAM architecture design methods and the applicable conditions. On the basis of the analysis, according to the characteristics of the 16Kb SRAM in this paper, the architecture design method of memory array partitioning is selected to realize the 16Kb SRAM. To select the optimal array partitioning method, two partitioning methods are simulated in this paper. Verify, compare its performance and implementation area, choose one of the best SRAM architecture implementation method; secondly, considering the accurate design of SRAM sequence generation circuit can effectively improve the overall speed of SRAM and reduce power consumption, this paper makes a detailed and in-depth analysis of Jingqing SRAM sequence generation circuit. There is a problem that the inverter delay can not effectively follow the discharge delay of the storage unit in order to realize the timing control of the inverter chain, and the process deviation is increasing in the deep submicron process, which is becoming more and more prominent. The two replication bit-line technologies use redundant replication columns and replication units to simulate the read operation of the storage unit to generate SRAM control signals. In capacitance ratio and current ratio replication bit-line technology, the units of replication columns are identical with the storage array units, ensuring that the parasitic capacitance of the replication column is identical with the parasitic capacitance of the storage array bit-line, and the replication unit reads. The operating current is the same as the current of the current read-operate unit, so it can accurately follow the SRAM read-operate discharge delay. The above two techniques can only ensure the accurate generation of the timing signal under the fixed power supply voltage. When the SRAM works in a certain voltage range, the capacitance ratio and current ratio technology are used to achieve the timing control when the power supply voltage is changed. In this paper, a programmable duplicate bit-line technology is creatively proposed for SRAM operating in a certain range of voltage to ensure that SRAM can accurately generate timing signals at all operating voltages. The simulation and test results show that the programmable duplicate bit-line proposed in this paper can be used to solve the problem of SRAM performance. The technology improves the performance of SRAM very well. Thirdly, through analyzing and comparing the structure and characteristics of the existing decoding circuit, this paper chooses full-static decoding logic to implement the 16Kb SRAM in this paper. Considering that the line delay can be compared with the gate delay in 65nm process, especially in SRAM where the pre-decoding to the secondary decoding takes a long interconnection, this paper discusses the logical path design method including the interconnection delay, and finally realizes the high-speed decoding in this paper. Code circuit.
The sixteen-kb SRAM realized in this paper has a read-out delay of 540 PS under typical voltage, which meets the design requirements. The results of the chip test under SMIC65nm process show that the sixteen-kb SRAM can operate in the voltage range of 0.8V-1.4V, the frequency range of 440MHz-1.62GHz, the typical power supply voltage of 1.2V, and the SRAM working speed reaches 1.22GH at room temperature. Z, the area is 22762.76 um 2, which is much smaller than 28826.512 um 2. In order to verify the validity of the programmable duplicate bit-line technology, this paper compares the SRAM realized by the new technology and the current-ratio duplicate bit-line technology. The results show that the highest specific frequency and current-ratio duplicate bit of the new technology can be achieved with the change of power supply voltage. Line technology improves 4.3%-9.5%.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333
【參考文獻】
相關(guān)博士學(xué)位論文 前1條
1 顧明;嵌入式SRAM性能模型與優(yōu)化[D];東南大學(xué);2006年
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