基于NAND閃存的固態(tài)盤關鍵技術研究
發(fā)布時間：2018-08-12 14:38
【摘要】：近半個世紀來,隨著計算機體系結構技術及芯片加工技術的不斷進步,計算機系統(tǒng)的CPU性能與IO性能的差距不斷擴大。計算機系統(tǒng)IO性能的瓶頸在于硬盤。這些年雖然磁盤容量有了迅速提升,但由于其存在機械旋轉結構,訪問速度提升有限,使得基于硬盤的存儲系統(tǒng)成為計算機系統(tǒng)的性能瓶頸之一。相比于傳統(tǒng)的硬盤,固態(tài)硬盤呈現(xiàn)出許多優(yōu)良的性能:低功耗,讀寫速度快,防震抗摔性好,無噪音,重量輕等,因此固態(tài)硬盤在許多領域已經開始替代傳統(tǒng)硬盤。然而,固態(tài)硬盤也繼承閃存的缺點,包括讀寫不對稱、寫前擦除、有限的擦除次數(shù)等。本文主要研究固態(tài)硬盤設計中的緩沖區(qū)管理算法和閃存轉換層算法,以減少對固態(tài)硬盤的寫和擦除次數(shù)。在緩沖區(qū)管理算法設計中,本文提出了一種面向頁級FTL的緩沖區(qū)管理算法——VBBMS(Virtual-Block-based Buffer Management Scheme)。首先,VBBMS將RAM分成隨機請求處理區(qū)和連續(xù)請求處理區(qū),分別用來處理隨機請求和連續(xù)請求;其次,VBBMS采用虛擬塊技術,盡可能存儲訪問頻率高的數(shù)據,并且對隨機請求進行重構,將隨機的、小的請求變成順序的、大的連續(xù)請求發(fā)送給SDFTL,以減少閃存的讀寫次數(shù)和優(yōu)化垃圾回收的效率;最后,連續(xù)請求處理區(qū)通過預取數(shù)據,利用請求的空間局部性,增加了緩沖區(qū)的命中率,進一步了提升系統(tǒng)的整體性能。實驗結果顯示,平均而言,VBBMS相比BPLRU算法,緩沖區(qū)命中率提高20.92%,響應時間減少23.93%,塊擦除次數(shù)減少13.38%;相比CFLRU算法,緩沖區(qū)命中率提高29.33%,響應時間減少28.09%,塊擦除次數(shù)減少48.77%;相比頁級LRU算法,緩沖區(qū)命中率提高44.16%,響應時間減少33.70%,塊擦除次數(shù)減少55.75%。在閃存轉換層算法設計中,本文提出一種基于分類處理的聚簇頁級閃存轉換層算法——CPFTL(Clustered Page-level Flash Translation Layer)。首先,CPFTL將地址映射緩存分為熱映射表緩存、冷映射表緩存和連續(xù)映射表緩存,分別用來緩存訪問頻繁的請求的映射項、訪問不頻繁的請求的映射項和高空間本地性的請求的映射項,有效提升了各類請求的處理能力。其次,為利用連續(xù)請求的空間本地性,CPFTL的連續(xù)映射表緩存預取多個連續(xù)的映射項,提高它對連續(xù)請求的響應性能。最后,為減少頁級映射算法的轉換頁讀寫開銷,CPFTL的冷映射表緩存采用聚簇策略,即將屬于同一轉換頁中的映射項進行聚簇,按簇進行LRU管理,當冷映射表緩存滿時,根據簇的映射項個數(shù)和LRU選取合適的簇剔除到閃存。實驗結果顯示,平均而言,CPFTL相比經典的DFTL算法,總體緩存命中率提高50.59%,響應時間減少24.43%,地址轉換頁操作次數(shù)減少82.87%,塊擦除次數(shù)減少29.35%;相比最新的SDFTL算法,總體緩存命中率提升9.88%,響應時間減少8.25%,地址轉換頁操作次數(shù)減少50.62%,閃存塊擦除次數(shù)減少9.26%。
[Abstract]:In the last half century, with the development of computer architecture technology and chip processing technology, the gap between CPU performance and IO performance of computer system is widening. The bottleneck of IO performance of computer system is hard disk. Although the disk capacity has increased rapidly in recent years, due to its mechanical rotation structure and limited access speed, the hard-disk storage system has become one of the performance bottlenecks of computer systems. Compared with the traditional hard disk, the solid-state hard disk presents many excellent performances: low power consumption, fast reading and writing speed, good shock resistance, no noise, light weight and so on. Therefore, the solid state hard disk has begun to replace the traditional hard disk in many fields. However, solid-state hard disk also inherits the disadvantages of flash memory, including reading and writing asymmetry, pre-write erasure, limited erasure times and so on. In this paper, buffer management algorithm and flash memory conversion layer algorithm in solid state hard disk design are studied to reduce the number of write and erase of solid state hard disk. In the design of buffer management algorithm, this paper proposes a new buffer management algorithm for page-level FTL named VBBMS (Virtual-Block-based Buffer Management Scheme). Firstly, RAM is divided into random request processing area and continuous request processing area, which are used to process random request and continuous request respectively. Secondly, VBBMS uses virtual block technology to store data with high access frequency as much as possible, and reconstructs random request. The random, small requests are sent to SDFTL in order to reduce the number of reads and writes in flash memory and optimize the efficiency of garbage collection. Finally, the continuous request processing area utilizes the spatial locality of the request by prefetching data. The hit ratio of buffer is increased, and the overall performance of the system is further improved. The experimental results show that, on average, compared with BPLRU algorithm, the hit rate of buffer increases 20.922.The response time decreases 23.933.The number of block erasure decreases 13.38. compared with CFLRU algorithm, VBBMS improves the hit rate of buffer by 20.922a, reduces the response time by 23.933.Compared with the CFLRU algorithm, The hit rate of buffer increases 29.33, the response time decreases 28.09, the number of block erasure decreases 48.77, compared with the page-level LRU algorithm, the hit ratio of buffer increases 44.16, the response time decreases 33.70, and the number of block erasure decreases 55.75. In the design of flash memory conversion layer algorithm, this paper presents a clustering page level flash conversion layer algorithm based on classification processing: CPFTL (Clustered Page-level Flash Translation Layer).) First of all, CPFTL divides the address mapping cache into hot map cache, cold map table cache and continuous mapping table cache, which are used to cache the mapping items that access frequent requests, respectively. To access the mapping items of infrequent requests and high spatial local requests, the processing ability of all kinds of requests is improved effectively. Secondly, in order to use the continuous mapping table of CPFTL to cache multiple consecutive mapping items, the response performance of CPFTL to continuous requests is improved. Finally, in order to reduce the conversion page reading and writing overhead of page-level mapping algorithm, the cold mapping table cache of CPFTL adopts clustering strategy, that is, the mapping items belonging to the same conversion page are clustered, and LRU is managed by cluster. When the cold mapping table is full, Select suitable cluster to flash memory according to the number of mapping items and LRU. The experimental results show that, on average, compared with the classical DFTL algorithm, the total cache hit ratio is increased by 50.59, the response time is reduced by 24.43, the number of operations on the address conversion page is reduced by 82.87, the number of block erasures is reduced by 29.35, and compared with the latest SDFTL algorithm, The total hit rate of cache increases 9.88, the response time decreases 8.25, the number of operations of address conversion page reduces 50.62and the number of flash block erasures decreases 9.26.
【學位授予單位】：杭州電子科技大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TP333
本文編號：2179360
[Abstract]:In the last half century, with the development of computer architecture technology and chip processing technology, the gap between CPU performance and IO performance of computer system is widening. The bottleneck of IO performance of computer system is hard disk. Although the disk capacity has increased rapidly in recent years, due to its mechanical rotation structure and limited access speed, the hard-disk storage system has become one of the performance bottlenecks of computer systems. Compared with the traditional hard disk, the solid-state hard disk presents many excellent performances: low power consumption, fast reading and writing speed, good shock resistance, no noise, light weight and so on. Therefore, the solid state hard disk has begun to replace the traditional hard disk in many fields. However, solid-state hard disk also inherits the disadvantages of flash memory, including reading and writing asymmetry, pre-write erasure, limited erasure times and so on. In this paper, buffer management algorithm and flash memory conversion layer algorithm in solid state hard disk design are studied to reduce the number of write and erase of solid state hard disk. In the design of buffer management algorithm, this paper proposes a new buffer management algorithm for page-level FTL named VBBMS (Virtual-Block-based Buffer Management Scheme). Firstly, RAM is divided into random request processing area and continuous request processing area, which are used to process random request and continuous request respectively. Secondly, VBBMS uses virtual block technology to store data with high access frequency as much as possible, and reconstructs random request. The random, small requests are sent to SDFTL in order to reduce the number of reads and writes in flash memory and optimize the efficiency of garbage collection. Finally, the continuous request processing area utilizes the spatial locality of the request by prefetching data. The hit ratio of buffer is increased, and the overall performance of the system is further improved. The experimental results show that, on average, compared with BPLRU algorithm, the hit rate of buffer increases 20.922.The response time decreases 23.933.The number of block erasure decreases 13.38. compared with CFLRU algorithm, VBBMS improves the hit rate of buffer by 20.922a, reduces the response time by 23.933.Compared with the CFLRU algorithm, The hit rate of buffer increases 29.33, the response time decreases 28.09, the number of block erasure decreases 48.77, compared with the page-level LRU algorithm, the hit ratio of buffer increases 44.16, the response time decreases 33.70, and the number of block erasure decreases 55.75. In the design of flash memory conversion layer algorithm, this paper presents a clustering page level flash conversion layer algorithm based on classification processing: CPFTL (Clustered Page-level Flash Translation Layer).) First of all, CPFTL divides the address mapping cache into hot map cache, cold map table cache and continuous mapping table cache, which are used to cache the mapping items that access frequent requests, respectively. To access the mapping items of infrequent requests and high spatial local requests, the processing ability of all kinds of requests is improved effectively. Secondly, in order to use the continuous mapping table of CPFTL to cache multiple consecutive mapping items, the response performance of CPFTL to continuous requests is improved. Finally, in order to reduce the conversion page reading and writing overhead of page-level mapping algorithm, the cold mapping table cache of CPFTL adopts clustering strategy, that is, the mapping items belonging to the same conversion page are clustered, and LRU is managed by cluster. When the cold mapping table is full, Select suitable cluster to flash memory according to the number of mapping items and LRU. The experimental results show that, on average, compared with the classical DFTL algorithm, the total cache hit ratio is increased by 50.59, the response time is reduced by 24.43, the number of operations on the address conversion page is reduced by 82.87, the number of block erasures is reduced by 29.35, and compared with the latest SDFTL algorithm, The total hit rate of cache increases 9.88, the response time decreases 8.25, the number of operations of address conversion page reduces 50.62and the number of flash block erasures decreases 9.26.
【學位授予單位】：杭州電子科技大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TP333
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