【摘要】：1999年，DDWG工作小組發(fā)布了數(shù)字視頻接口標(biāo)準(zhǔn)DVI1.0標(biāo)準(zhǔn)，DVI技術(shù)的出現(xiàn)，革新了整個(gè)視頻接口技術(shù)和市場(chǎng)。DVI作為一種優(yōu)秀的視頻接口技術(shù)，一經(jīng)提出，就迅速得到世界范圍內(nèi)業(yè)界人士和廠商的大力支持，經(jīng)過十四年的發(fā)展，如今DVI接口在視頻領(lǐng)域中的應(yīng)用非常廣泛。 DVI接口采用TMDS傳輸協(xié)議，支持從VGA到UXGA的顯示標(biāo)準(zhǔn)，單條TMDS鏈路時(shí)鐘頻率為25MHz～165MHz，數(shù)據(jù)速率為250Mbps～1.65Gbps。本文基于DVI1.0標(biāo)準(zhǔn)，對(duì)TMDS數(shù)據(jù)傳輸模式、TMDS鏈路結(jié)構(gòu)以及DVI接口系統(tǒng)結(jié)構(gòu)進(jìn)行分析，給出了DVI接收端數(shù)據(jù)流向的功能框圖，并且針對(duì)各個(gè)模塊進(jìn)行功能分析，重點(diǎn)研究了DVI接收端模擬部分電路的實(shí)現(xiàn)，主要包括三個(gè)部分：高速差分接收單元、3倍過采樣數(shù)據(jù)恢復(fù)電路和12相等相位差時(shí)鐘輸出電荷泵鎖相環(huán)電路。詳細(xì)介紹這些功能模塊的電路實(shí)現(xiàn)原理，，并且在仔細(xì)研究常用電路結(jié)構(gòu)性能的基礎(chǔ)上，對(duì)電平轉(zhuǎn)換電路、鑒頻鑒相器、電荷泵、壓控振動(dòng)器等傳統(tǒng)電路結(jié)構(gòu)分別進(jìn)行優(yōu)化，提出創(chuàng)新解決方案。 本文采用SMIC0.11μm混合工藝，使用Cadence公司的Virtuoso工具實(shí)現(xiàn)電路設(shè)計(jì)； Spingsoft公司的Laker工具完成版圖設(shè)計(jì)；整體版圖面積為264x145μm2。使用Synopsys公司的Hspice軟件完成對(duì)電路的前仿真和版圖的后仿真。后仿真結(jié)果表明，電路性能比較理想，完全能夠滿足DVI1.0標(biāo)準(zhǔn)數(shù)據(jù)傳輸要求。VGA分辨率模式時(shí)，接收時(shí)鐘頻率為25MHz，數(shù)據(jù)速率為250Mbps，PLL在3.6μs內(nèi)鎖定，系統(tǒng)在5.3μs內(nèi)穩(wěn)定工作，時(shí)鐘信號(hào)周期間抖動(dòng)峰-峰值為1.36%； UXGA分辨率模式時(shí)，接收時(shí)鐘頻率為165MHz，數(shù)據(jù)速率為1.65Gbps，PLL在2μs內(nèi)鎖定，系統(tǒng)在4.5μs內(nèi)穩(wěn)定工作，時(shí)鐘信號(hào)周期間抖動(dòng)峰-峰值為0.59%。
[Abstract]:In 1999, the Digital Video Interface Standard (DVI1.0) was released by the working Group of DWG, which revolutionized the whole video interface technology and the market. DVI as a kind of excellent video interface technology, once it was put forward, After 14 years of development, the DVI interface is widely used in the field of video. The DVI interface uses TMDS transport protocol. It supports the display standard from VGA to UXGA. The clock frequency of single TMDS link is 25MHz / 165MHz and the data rate is 250Mbps1.65Gbps. Based on the DVI1.0 standard, this paper analyzes the link structure of TMDS data transmission mode and the structure of DVI interface system, gives the function block diagram of the data flow direction of DVI receiver, and analyzes the function of each module. This paper focuses on the realization of analog circuit in DVI receiver, which consists of three parts: high speed differential receiving unit 3 times oversampling data recovery circuit and 12 equal phase difference clock output charge pump phase-locked loop circuit. The circuit realization principle of these functional modules is introduced in detail. On the basis of careful study of the common circuit structure and performance, the traditional circuit structures, such as level conversion circuit, frequency discriminator, charge pump, voltage controlled vibrator and so on, are optimized respectively. Propose innovative solutions. In this paper, the SMIC0.11 渭 m hybrid technology is used to realize the circuit design using the Virtuoso tool of Cadence Company, and the Laker tool of Spingsoft Company to complete the layout design. The overall layout area is 264x145 渭 m2. The Hspice software of Synopsys Company is used to finish the pre-simulation and post-emulation of the circuit. The simulation results show that the circuit performance is ideal and can meet the requirements of DVI1.0 standard data transmission. The receiving clock frequency is 25 MHz, the data rate is 250 MbpsPLL locked in 3.6 渭 s, and the system works stably in 5.3 渭 s. In the UXGA resolution mode, the received clock frequency is 165MHz, the data rate is 1.65GbpsPLL is locked within 2 渭 s, the system works stably within 4.5 渭 s, and the jitter peak is 0.59mm during the clock signal cycle.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP334.7;TN432

【參考文獻(xiàn)】

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本文編號(hào)：2146520