【摘要】：隨著時(shí)代的進(jìn)步和科技的發(fā)展,通用的處理芯片如FPGA、DSP、PowerPC等發(fā)展迅猛,然而由于高性能嵌入式實(shí)時(shí)處理平臺是由FPGA、DSP、存儲設(shè)備、IO等處理部件組成的綜合化的系統(tǒng),通過單獨(dú)提高某個(gè)處理器的性能并不能滿足整體性能的提升要求。例如以PCI、VME為代表的傳統(tǒng)總線已經(jīng)在一定程度上阻礙了嵌入式處理平臺性能的提升,目前以串行RapidIO為代表的新的總線結(jié)構(gòu)在一定程度上能夠增大總線帶寬和數(shù)據(jù)傳輸速率。因此,基于RapidIO的高性能嵌入式實(shí)時(shí)處理平臺的研究就顯得格外的重要了。 論文是針對某企業(yè)所承擔(dān)的預(yù)研科研課題實(shí)現(xiàn)基于RapidIO嵌入式實(shí)時(shí)系統(tǒng)。論文首先簡單的介紹了嵌入式處理平臺研究的課題意義及國內(nèi)外現(xiàn)狀,其次詳細(xì)分析嵌入式處理平臺軟硬件構(gòu)架及軟硬件的總體設(shè)計(jì),硬件電路設(shè)計(jì)包含F(xiàn)PGA、DSP、PowerPC等高性能處理器,以及除串行RapidIO之外的CAN總線、RS485總線、光纖等通訊接口,電源設(shè)計(jì)、電路調(diào)試,最后實(shí)現(xiàn)了嵌入式平臺的硬件設(shè)計(jì)；并且在該硬件平臺上移植了Vxworks操作系統(tǒng),然而由于Vxworks操作系統(tǒng)啟動(dòng)時(shí)間非常的緩慢,影響嵌入式處理平臺的整體性能,筆者通過對板級支持包的理解,分析了Vxworks操作系統(tǒng)的整體啟動(dòng)過程及啟動(dòng)的時(shí)間分布。論文通過實(shí)現(xiàn)對板級支持包的修改提出了一種集安全性、高效性于一體的操作系統(tǒng)啟動(dòng)方案,較好的完成了操作系統(tǒng)的啟動(dòng)優(yōu)化設(shè)計(jì)。筆者通過軟件程序設(shè)計(jì)完成了軟件的在線更新,使后續(xù)的維護(hù)和升級更加便捷。論文通過搭建一個(gè)RapidIO通信環(huán)境并與千兆以太網(wǎng)進(jìn)行對比,分析了RapidIO及以太網(wǎng)的性能差異和工作方式異同,驗(yàn)證結(jié)構(gòu)實(shí)現(xiàn)RapidIO整體性能. 最后,論文總結(jié)了嵌入式處理平臺開發(fā)的一些要點(diǎn),分析了阻礙嵌入式發(fā)展的一些因素,本文進(jìn)行了一個(gè)通用的基于RapidIO的高性能嵌入式實(shí)時(shí)處理平臺的研究,具有一定的使用意義及借鑒的價(jià)值。
[Abstract]:With the progress of the times and the development of science and technology, the general processing chips such as FPGA DSPO PowerPC have been developed rapidly. However, the embedded real-time processing platform with high performance is a comprehensive system composed of FPGA DSPs, storage devices and so on. Improving the performance of a single processor does not meet the overall performance requirements. For example, the traditional bus represented by PCI VME has hindered the performance improvement of embedded processing platform to some extent. At present, the new bus architecture, represented by serial RapidIO, can increase the bus bandwidth and data transmission rate to a certain extent. Therefore, the research of high performance embedded real-time processing platform based on RapidIO is especially important. In this paper, the embedded real-time system based on RapidIO is implemented for an enterprise. Firstly, this paper introduces the significance of embedded processing platform research and the current situation at home and abroad. Secondly, the hardware and software architecture of embedded processing platform and the overall design of hardware and software are analyzed in detail. The hardware circuit design includes FPGA DSP PowerPC and other high-performance processors. Besides serial RapidIO, CAN bus RS485 bus, optical fiber and other communication interfaces, power supply design, circuit debugging, the hardware design of embedded platform are realized, and the Vxworks operating system is transplanted on the hardware platform. However, because the startup time of Vxworks operating system is very slow, which affects the whole performance of embedded processing platform, the author analyzes the whole startup process and startup time distribution of Vxworks operating system through the understanding of board level support package. This paper proposes an operating system startup scheme which integrates security and efficiency through the modification of the board support package, and completes the optimization design of the operating system. The author completes the online update of the software through the software programming, which makes the subsequent maintenance and upgrade more convenient. By setting up a RapidIO communication environment and comparing it with Gigabit Ethernet, this paper analyzes the performance difference and working mode of RapidIO and Ethernet, and verifies that the whole performance of RapidIO is realized by the structure. Finally, the paper summarizes some key points of embedded processing platform development, analyzes some factors that hinder the development of embedded platform, and carries on the research of a general high performance embedded real-time processing platform based on RapidIO. Has certain use significance and the reference value.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP368.1

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 何賓,韓月秋;高性能信號處理系統(tǒng)體系結(jié)構(gòu)的研究與實(shí)現(xiàn)[J];北京理工大學(xué)學(xué)報(bào);2003年06期

2 紀(jì)斌;鄭志國;;基于PowerPC的RapidIO高速串行通信設(shè)計(jì)與實(shí)現(xiàn)[J];電訊技術(shù);2011年03期

3 孫亮;楊斌;鐘瑜;;基于MPC8548E的嵌入式實(shí)時(shí)系統(tǒng)自舉優(yōu)化設(shè)計(jì)[J];電訊技術(shù);2012年02期

4 郭磊;用VC開發(fā)Windows Socket網(wǎng)絡(luò)程序[J];電子科技;2001年02期

5 朱堅(jiān);徐光輝;朱利利;;基于Serial RapidIO的高速實(shí)時(shí)數(shù)據(jù)采集處理系統(tǒng)[J];電子質(zhì)量;2008年10期

6 鄧豹;趙小冬;;基于串行RapidIO的嵌入式互連研究[J];航空計(jì)算技術(shù);2008年03期

7 解月江,張梅;Vx Works下設(shè)備驅(qū)動(dòng)技術(shù)研究[J];航天控制;2004年06期

8 陳麗華,潘健,倪明,柴小麗;新型總線技術(shù)——RACEway和RapidIO概述[J];計(jì)算機(jī)工程;2003年14期

9 李瓊;郭御風(fēng);劉光明;劉濤;;I/O互聯(lián)技術(shù)及體系結(jié)構(gòu)的研究與發(fā)展[J];計(jì)算機(jī)工程;2006年12期

10 黃亮;劉福巖;;基于RapidIO和存儲映射的高速互連網(wǎng)絡(luò)[J];計(jì)算機(jī)工程;2008年14期

相關(guān)碩士學(xué)位論文 前2條

1 舒宗杰;SCA電臺信號處理模塊的設(shè)計(jì)與實(shí)現(xiàn)[D];西南交通大學(xué);2011年

2 潘靈;基于RapidIO總線的進(jìn)程間通信系統(tǒng)的研究與實(shí)現(xiàn)[D];電子科技大學(xué);2009年

，

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