本文選題：DSP + 指令Cache�。� 參考：《江南大學》2012年碩士論文

【摘要】：高速緩沖存儲器(Cache)有效彌補了處理器與主存儲器之間的速度差距,加快了處理器對存儲器的讀寫速度,提高了DSP(Digital Signal Processor)系統(tǒng)性能。但是Cache因其面積大、速度快、訪問頻繁,被視為處理器芯片功耗的主要來源。如何設計一個高性能低功耗的Cache,對于DSP處理器整體性能有著重要的意義,已經(jīng)成為了一個熱點問題。 本文設計了一種指令Cache:通過添加一個具有重裝功能的Line Buffer,有效減少了CPU對Cache的訪問次數(shù),從而降低了指令Cache的相關功耗。并且在Cache發(fā)生缺失時,重裝控制單元能在6個時鐘周期內(nèi)將片外存儲單元中的指令送到CPU取指單元,有效提高了指令Cache的性能。對于指令Cache的設計主要包括基本參數(shù)的設計,指令Cache體系結(jié)構(gòu)的設計,各個功能模塊的設計,以及Line Buffer的設計。其中,在對指令Cache設計時,需要根據(jù)DSP處理器的具體特征合理規(guī)劃好工作流程,減少指令Cache命中時間。 整個指令Cache的設計采用自頂向下的設計流程,以硬件描述語言VHDL作為輸入工具進行指令Cache的設計。使用Mentor公司的Modelsim對設計進行功能仿真,以SYNOPSYS公司的綜合工具Design Compiler對指令Cache部分進行邏輯綜合。綜合和仿真結(jié)果表明:整個指令Cache的設計實現(xiàn)了所有預期功能,滿足了路徑延時的要求,在最壞情況下最長路徑延時為1.66ns。通過運行3種基準測試程序得出:Line Buffer可以使CPU對指令Cache訪問頻率減少35%,有效降低了指令Cache的功耗。目前該設計已成功應用于32位的高端DSP中,并使其整體功耗位于0.5mW/MIPS以內(nèi)。
[Abstract]:Cache can effectively bridge the speed gap between the processor and the main memory, accelerate the speed of the processor to read and write the memory, and improve the performance of the DSP (Digital signal processor) system. However, cache is regarded as the main source of power consumption because of its large area, high speed and frequent access. How to design a high performance and low power Cacheis of great significance for the overall performance of DSP processors has become a hot issue. This paper designs an instruction Cache. by adding a reload line buffer, the number of CPU access to Cache is reduced effectively, and the related power consumption of instruction cache is reduced. When cache is missing, the reload control unit can send the instructions from the off-chip memory unit to the CPU in six clock cycles, which improves the performance of the instruction cache effectively. The design of instruction cache mainly includes the design of basic parameters, the architecture of instruction cache, the design of each function module, and the design of Line buffer. In the design of instruction cache, it is necessary to reasonably plan the workflow according to the specific characteristics of DSP processor and reduce the hit time of instruction cache. The whole instruction cache design adopts the top-down design flow, and uses the hardware description language VHDL as the input tool to design the instruction cache. The function of the design is simulated by Modelsim of Mentor Company, and the instruction Cache part is logically synthesized by Design Compiler, a Synthetical tool of SYNOPSYS. The results of synthesis and simulation show that the design of the instruction cache achieves all the expected functions and meets the requirement of path delay. In the worst case, the longest path delay is 1.66 ns. By running three kinds of benchmark programs, it is concluded that: line buffer can reduce the frequency of CPU access to instruction Cache by 35 times, and effectively reduce the power consumption of instruction cache. At present, the design has been successfully applied to 32 bit high end DSP, and the overall power consumption is within 0.5 MW / MIPS.
【學位授予單位】：江南大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP368.1

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本文編號：2068867