發(fā)布時(shí)間：2018-06-26 01:43

  本文選題：G.hn + 電力線通信　； 參考：《華南理工大學(xué)》2013年碩士論文

【摘要】：G.hn是國際電信聯(lián)盟(ITU)為正在高速發(fā)展的有線互聯(lián)的家庭網(wǎng)絡(luò)制定的標(biāo)準(zhǔn),該標(biāo)準(zhǔn)同時(shí)支持電話線、同軸電纜和電力線三種傳輸介質(zhì),而電力線是其中最為復(fù)雜的介質(zhì)。其物理層的傳輸速率理論上可達(dá)1Gbit/s,預(yù)期將成為新時(shí)期家庭網(wǎng)絡(luò)有線互聯(lián)技術(shù)的基礎(chǔ)。G.hn標(biāo)準(zhǔn)采用OFDM調(diào)制技術(shù),而快速傅里葉變換(FFT)是該技術(shù)的核心。因此在本論文中,我們創(chuàng)新設(shè)計(jì)了一個(gè)具有高處理速度、高吞吐率、高集成度、高靈活性、高精度和接口簡單標(biāo)準(zhǔn)化等優(yōu)點(diǎn)的,適用于G.hn標(biāo)準(zhǔn)中電力線信道的實(shí)序列FFT處理器。具體地說,本論文主要完成了以下三個(gè)方面的創(chuàng)新工作： 第一,本論文研究了電力線信道的特性,并搭建了一個(gè)具有頻率選擇性、顯著衰減并且隨時(shí)間變化的電力線信道模型,用于FFT算法仿真與誤差分析。 第二,本論文研究了FFT的Radix-2/4/8算法,比較了各種算法的優(yōu)缺點(diǎn),選擇了Radix-4作為FFT處理器的基本算法。利用實(shí)序列FFT算法的周期性和對稱性,提出了一種創(chuàng)新算法,可以使運(yùn)算量減少近一半,大大提高運(yùn)算效率和處理速度。接著,為提高處理器的運(yùn)算精度和減少硬件面積,采用Stage-based塊浮點(diǎn)(BFP)算法用于IFFT/FFT數(shù)據(jù)的存儲(chǔ)和運(yùn)算。最后,使用Matlab對Radix-4BFP FFT算法進(jìn)行仿真,對不同的定點(diǎn)方案做誤差分析,最終找到了輸入輸出數(shù)據(jù)和旋轉(zhuǎn)因子的最佳精度要求。 第三,本論文研究了FFT處理器現(xiàn)有的架構(gòu),透徹分析了流水線式和存儲(chǔ)器式兩種架構(gòu)的優(yōu)缺點(diǎn),設(shè)計(jì)了適用于G.hn標(biāo)準(zhǔn)OFDM系統(tǒng)的,基于乒乓RAM、流水線的實(shí)序列塊浮點(diǎn)FFT處理器架構(gòu),結(jié)合了流水線式和存儲(chǔ)器式兩種架構(gòu)的優(yōu)點(diǎn),使得本論文設(shè)計(jì)的FFT處理器具有高處理速度和高吞吐率的優(yōu)點(diǎn)。接著,基于以上算法原理及架構(gòu).使用硬件描述語言Verilog,完成了FFT處理器的電路設(shè)計(jì),并使用可重用的VMM架構(gòu)進(jìn)行了功能驗(yàn)證,提高了驗(yàn)證效率。最后采用TSMC0.18um1P6M工藝進(jìn)行實(shí)現(xiàn),面積約為6.3mm2,該處理器最高工作頻率可達(dá)383MHz,即本論文設(shè)計(jì)的FFT處理器完全滿足G.hn系統(tǒng)的要求。
[Abstract]:G. hn is a standard developed by the International Telecommunication Union (ITU) for a rapidly developing wired home network. The standard supports three transmission mediums: telephone line, coaxial cable and power line, among which power line is the most complex medium. The transmission rate of the physical layer can reach 1Gbit / s theoretically, which is expected to become the basis of the wired interconnection technology of the home network in the new era. The OFDM modulation technology is adopted in the G.hn standard, and the fast Fourier transform (FFT) is the core of the technology. Therefore, in this thesis, we have innovatively designed a real sequence FFT processor with high processing speed, high throughput, high integration, high flexibility, high precision and simple standardization of interface, which is suitable for the power line channel in G.hn standard. Specifically, this thesis mainly completes the following three aspects of innovation: first, this paper studies the characteristics of power line channel, and builds a frequency selective one. The power line channel model, which attenuates significantly and varies with time, is used for FFT algorithm simulation and error analysis. Secondly, this paper studies the Radix-2 / 4 / 8 algorithm of FFT, compares the advantages and disadvantages of various algorithms, and selects Radix-4 as the basic algorithm of FFT processor. Based on the periodicity and symmetry of the real sequence FFT algorithm, an innovative algorithm is proposed, which can reduce the computation cost by nearly half and greatly improve the operation efficiency and processing speed. Then, in order to improve the processing accuracy and reduce the hardware area, Stage-based block floating-point (BFP) algorithm is used to store and compute the IFFT / FFT data. Finally, the Radix-4BFP FFT algorithm is simulated with Matlab, and the error of different fixed-point schemes is analyzed. Finally, the best precision requirements of input and output data and rotation factor are found. Thirdly, this paper studies the existing architecture of FFT processor, thoroughly analyzes the advantages and disadvantages of pipeline and memory architecture, and designs an OFDM system suitable for G. hn standard. Based on ping-pong RAM and pipelined real sequence block floating-point FFT processor architecture, which combines the advantages of pipeline and memory architecture, the FFT processor designed in this paper has the advantages of high processing speed and high throughput. Then, based on the above algorithm principle and architecture. The circuit design of FFT processor is completed by using the hardware description language Verilog. and the function verification is carried out by using reusable VMM architecture, which improves the efficiency of verification. Finally, a TSMC 0.18um1P6M process is used, with an area of about 6.3mm ~ 2, and the maximum operating frequency of the processor can reach 383MHz. The FFT processor designed in this paper can fully meet the requirements of the G.hn system.
【學(xué)位授予單位】：華南理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

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本文編號(hào)：2068497