本文選題：FPGA + SATA��； 參考：《南京大學(xué)》2013年碩士論文

【摘要】：并行總線PATA由提出至今已經(jīng)有快30年的歷史,如今它的缺陷已經(jīng)嚴(yán)重阻礙了存儲性能的進(jìn)一步發(fā)展,目前已經(jīng)被SATA總線所取代。SATA作為新一代的硬盤接口協(xié)議,已經(jīng)發(fā)展到了第三代,傳輸速率從第一代的150MB/s已經(jīng)發(fā)展到了600MB/s,并且采用的是點對點數(shù)據(jù)傳輸,內(nèi)置糾錯校驗單元,支持熱插拔,能夠支持RAID模式等。SATA在存儲領(lǐng)域已經(jīng)被廣泛使用,目前國際上只有2家公司會提供付費(fèi)的高性能SATA IP,國內(nèi)尚無對于SATA IP的開發(fā),因此設(shè)計面向FPGA應(yīng)用的SATA IP具有重要意義。 本論文對SATA協(xié)議整體進(jìn)行了詳細(xì)的分析,分析了SATA軟核構(gòu)建的層次結(jié)構(gòu)。將設(shè)備端的軟核層次劃分成應(yīng)用層、傳輸層、鏈路層和物理層四個層次；在此基礎(chǔ)上著重闡述協(xié)議物理層次的設(shè)計,通過Groundhog實現(xiàn)SATA協(xié)議中的鏈接層、傳輸層和命令層。介紹了SATA協(xié)議的NCQ功能,并且對基于FPGA的SATA IP進(jìn)行了優(yōu)化設(shè)計和測試,通過數(shù)據(jù)對比表明優(yōu)化方式的優(yōu)越性。 論文主要致力于實現(xiàn)目前主流的SATA協(xié)議的基礎(chǔ)上,通過排隊序列的算法使SATA IP的讀取速率平均提高了50%～140%,同時減少了功耗和硬盤的損耗。
[Abstract]:PATA, a parallel bus, has been proposed for nearly 30 years. Now, its defects have seriously hindered the further development of storage performance. At present, it has been replaced by SATA bus as a new generation of hard disk interface protocol. In the third generation, the transmission rate has grown from the first 150 MB / s to 600 MB / s, using point-to-point data transmission, with built-in error correction units that support hot swapping. It has been widely used in storage field to support raid mode and so on. At present, only 2 companies in the world will provide high performance SATA IPs for payment. There is no development of SATA IP in China, so it is of great significance to design SATA IP for FPGA applications. In this paper, the whole SATA protocol is analyzed in detail, and the hierarchical structure of SATA soft core is analyzed. The soft core layer of the device is divided into application layer, transmission layer, link layer and physical layer, on the basis of which, the design of protocol physical layer is emphasized, and the link layer, transmission layer and command layer in SATA protocol are realized by Groundhog. This paper introduces the NCQ function of SATA protocol, and optimizes the design and test of SATA IP based on FPGA. Based on the implementation of the current mainstream SATA protocol, the average reading rate of SATA IP is increased by the queueing sequence algorithm, and the power consumption and hard disk loss are reduced at the same time.
【學(xué)位授予單位】：南京大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333.35

【參考文獻(xiàn)】

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本文編號：2069044