本文選題：反熔絲 + PROM存儲器��； 參考：《東南大學(xué)》2016年碩士論文

【摘要】：一次性可編程(OTP)存儲器一旦寫入數(shù)據(jù),存儲單元就一直是擊穿或者熔斷的狀態(tài)。這種擊穿或者熔斷的編程條件(如高電壓)在存儲器正常工作時是不存在的,從而保證了OTP存儲器較高的可靠性。OTP存儲器可以由用戶自主進(jìn)行一次編程,而且在未編程的區(qū)域,可以通過一定的數(shù)據(jù)管理算法對數(shù)據(jù)進(jìn)行更新和替換,增加了數(shù)據(jù)存儲空間使用的靈活性,且其設(shè)計簡單、成本較低,在嵌入式系統(tǒng)、航空航天以及密鑰存儲等應(yīng)用中非常適用。本文設(shè)計的基于反熔絲存儲單元的OTP存儲器包含存儲陣列、地址譯碼器、編程電路和讀取電路、錯誤檢測與糾正電路、電源模塊和邏輯控制模塊等。本文首先研究了反熔絲存儲單元,比較了三種反熔絲存儲單元結(jié)構(gòu)之后選擇了單晶體管反熔絲存儲單元,這種結(jié)構(gòu)在讀取速度和存儲容量上有明顯的優(yōu)勢,非常適合于大容量存儲器產(chǎn)品的應(yīng)用需求。研究了存儲單元的存儲機(jī)理、擊穿特性以及擊穿之后的電阻特性,完成了存儲陣列的設(shè)計。然后,論文對存儲器的外圍電路進(jìn)行了分析與設(shè)計。采用了多維譯碼的方式,方面配合了存儲陣列的排布,另一方面有效地減小了延時；設(shè)計了編程電路和讀取電路以實現(xiàn)數(shù)據(jù)的寫入和讀出；為了盡可能地保證存儲數(shù)據(jù)的準(zhǔn)確性和可靠性,加入了錯誤檢測與糾正和冗余功能；設(shè)計了低壓差線性穩(wěn)壓器(LDO)為數(shù)據(jù)的讀取提供2.4V的讀電壓,該LDO采用了單晶體管控制結(jié)構(gòu),以改善其瞬態(tài)響應(yīng)。最后用Spectre和Nanosim對系統(tǒng)進(jìn)行了仿真。仿真結(jié)果表明該反熔絲可編程只讀存儲器各項功能和性能均能滿足預(yù)期要求。本文在常規(guī)商用工藝上實現(xiàn)了存儲容量為16k比特的反熔絲可編程只讀存儲器,該存儲器可以用于為主控芯片(如CPU)提供配置數(shù)據(jù)和重要程序數(shù)據(jù)的存儲。
[Abstract]:Once the data is written, the memory cell is always a breakdown or fuse state. This breakdown or fuse programming condition, such as high voltage, does not exist when the memory is working properly, thus ensuring the high reliability of the OTP memory. The OTP memory can be programmed by the user on his own initiative, and in unprogrammed areas, The data can be updated and replaced by a certain data management algorithm, which increases the flexibility of the use of data storage space, and its design is simple, the cost is low, in the embedded system, Aerospace and key storage and other applications are very suitable. The OTP memory based on anti-fuse memory cell is designed in this paper, which includes memory array, address decoder, programming circuit and read circuit, error detection and correction circuit, power supply module and logic control module. In this paper, we first study the anti-fuse memory cell, compare three kinds of anti-fuse memory cell structure, and choose the single-transistor anti-fuse memory cell. This structure has obvious advantages in reading speed and storage capacity. It is very suitable for the application of mass storage products. The memory mechanism, breakdown characteristics and resistance characteristics of the memory cell are studied, and the design of the memory array is completed. Then, the peripheral circuit of the memory is analyzed and designed. The multi-dimension decoding method is adopted, the storage array is arranged in the aspect, on the other hand, the delay is reduced effectively, and the programming circuit and the reading circuit are designed to realize the data writing and reading. In order to ensure the accuracy and reliability of the stored data as much as possible, the functions of error detection, correction and redundancy are added, and a low voltage differential linear voltage regulator (LDO) is designed to provide a reading voltage of 2.4 V for data reading. The LDO adopts a single-transistor control structure. To improve its transient response. Finally, the system is simulated with Spectre and Nanosim. The simulation results show that the function and performance of the anti-fuse programmable read-only memory can meet the expected requirements. In this paper, an anti-fuse programmable read-only memory with a storage capacity of 16k bits is implemented in a conventional commercial process. The memory can be used to store configuration data and important program data for the main control chip (such as CPU).
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TP333

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本文編號：2039103