本文選題：多態(tài)陣列處理器 + 眾核��； 參考：《西安郵電大學(xué)》2014年碩士論文

【摘要】：通過在單個芯片上集成成千上萬個簡單處理核來獲得高性能和高吞吐量,已成為目前計(jì)算機(jī)體系結(jié)構(gòu)研究的熱點(diǎn)。雖然眾核芯片上的單個簡單處理核不具備復(fù)雜控制邏輯,在開發(fā)指令級并行方面存在很多難點(diǎn),但是同一芯片上的眾多簡單處理核協(xié)同工作能獲得復(fù)雜多核所不能獲得的指令級并行度。本文通過對流行的計(jì)算機(jī)體系結(jié)構(gòu)進(jìn)行了詳細(xì)分析,針對其在并行計(jì)算開發(fā)方面的難點(diǎn),深入研究了眾核多態(tài)陣列處理器--PAAG(Polymorphic Array Architecture for Graphics and image processing)在并行計(jì)算方面的特性,通過結(jié)合線程級并行、數(shù)據(jù)級并行以及指令級并行等多種并行計(jì)算模式來挖掘程序中的并行性。 本文以具有廣泛應(yīng)用的圖像處理為主要研究對象,通過對常用的圖像處理算法進(jìn)行深入研究和分類,挖掘其中的并行處理共性,并以PAAG為硬件開發(fā)平臺,充分挖掘圖像處理領(lǐng)域中大規(guī)模并行計(jì)算的能力,從時空滿載的目標(biāo)角度來使計(jì)算任務(wù)最大并行化,以此充分利用眾核上的硬件資源,使圖像處理程序在多態(tài)陣列處理器中獲得盡可能高的加速比。 本文最后推導(dǎo)了PAAG陣列處理器在圖像處理算法中的加速比計(jì)算公式,通過實(shí)驗(yàn)數(shù)據(jù)說明了眾核PAAG陣列處理器在并行計(jì)算方面所具有的優(yōu)勢,并總結(jié)出在眾核PAAG陣列處理器中進(jìn)行深度并行計(jì)算的方法。
[Abstract]:The integration of thousands of simple processing cores on a single chip to achieve high performance and high throughput has become a hot topic in the research of computer architecture. Although a single processing core on a multi-core chip does not have complex control logic, there are many difficulties in developing instruction level parallelism. However, many simple processing cores on the same chip can work together to obtain instruction level parallelism that complex multi-core can not achieve. In this paper, the popular computer architecture is analyzed in detail, and the characteristics of polymorphic Array Architecture for Graphics and image processing) with multi-core polymorphic array processor in parallel computing are deeply studied in view of its difficulties in parallel computing development. The parallelism in programs is mined by combining thread level parallelism, data level parallelism and instruction level parallelism. This paper takes the widely used image processing as the main research object, through the in-depth research and classification of the commonly used image processing algorithms, mining the common parallel processing, and taking PAAG as the hardware development platform. Fully mining the ability of large-scale parallel computing in the field of image processing to maximize parallelization of computing tasks from the point of view of space-time full load, so as to make full use of the hardware resources on multiple cores. Enables image processors to achieve the highest speedup possible in polymorphic array processors. Finally, the speedup calculation formula of PAAG array processor in image processing algorithm is deduced. The advantages of multi-core paag array processor in parallel computing are illustrated by experimental data. The method of deep parallel computing in multi-core PAAG array processor is summarized.
【學(xué)位授予單位】：西安郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP332

【參考文獻(xiàn)】

相關(guān)博士學(xué)位論文 前2條

1 陳鋼;眾核GPU體系結(jié)構(gòu)相關(guān)技術(shù)研究[D];復(fù)旦大學(xué);2011年

2 洪春濤;眾核處理器編程模式關(guān)鍵技術(shù)研究[D];清華大學(xué);2011年

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本文編號：2038659