本文選題：流處理器 + 流核心��； 參考：《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：片上集成傳統(tǒng)多核處理器（以桌面CPU為代表）和流多核處理器（以GPU為代表）已成為多核處理器的發(fā)展方向，但異構(gòu)的結(jié)構(gòu)導(dǎo)致功耗很大，分離的存儲也會導(dǎo)致通信瓶頸，故本項目組提出同構(gòu)通用流處理器的體系結(jié)構(gòu)。該結(jié)構(gòu)是由四個流核心共享前端構(gòu)成一個流多核，根據(jù)應(yīng)用程序來配置CPU和SP中流多核的數(shù)目。同構(gòu)通用流處理器不僅要面向高性能計算應(yīng)用，對圖形圖像處理也需要能快速處理，這些對處理器的運(yùn)算部件提出了很高的要求。 本課題完成了64位流核心運(yùn)算部件的設(shè)計與實現(xiàn)，主要工作和創(chuàng)新點包括： 1、對于整數(shù)運(yùn)算部件，充分利用圖形圖像處理的數(shù)據(jù)窄位寬的特性，完成了加/減法單元、乘法單元的設(shè)計，這兩個運(yùn)算單元與浮點運(yùn)算共享前導(dǎo)零邏輯來靈活處理不同位寬運(yùn)算，，從而有效利用資源，減少計算延遲。還完成了整數(shù)運(yùn)算部件中比較單元、移位單元、除法單元的設(shè)計與VHDL代碼實現(xiàn)。 2、對于浮點運(yùn)算部件，完成了浮點加/減單元、浮點乘法單元、浮點/整數(shù)轉(zhuǎn)換單元、浮點除法單元、浮點開方單元的設(shè)計與實現(xiàn)，并實現(xiàn)了浮點加/減、浮點乘法和浮點/整數(shù)轉(zhuǎn)換操作的流水化設(shè)計，提升了浮點運(yùn)算部件的處理能力。 3、利用Xilinx公司的ISE12.1開發(fā)軟件，完成了64位流核心的系統(tǒng)驗證平臺設(shè)計。通過對各個運(yùn)算單元添加測試激勵來驗證它們的功能正確性，通過系統(tǒng)執(zhí)行多條浮點指令來驗證流水化處理的正確性。驗證的結(jié)果表明運(yùn)算部件的設(shè)計實現(xiàn)了處理器要求的運(yùn)算操作，并能夠在整個流核心系統(tǒng)中正常運(yùn)行。通過軟件自動綜合，得到了運(yùn)算部件的相關(guān)性能參數(shù)。
[Abstract]:The integration of traditional multi-core processors (represented by desktop CPU) and stream multi-core processors (represented by GPU) has become the development direction of multi-core processors. However, heterogeneous architectures lead to high power consumption, and separate storage also leads to communication bottlenecks. Therefore, the project team proposes the architecture of the isomorphic universal stream processor. The structure is composed of four stream cores to share the front end, and the number of stream multicore in CPU and SP is configured according to the application program. The isomorphic general stream processor not only needs high performance computing applications, but also needs to be able to process graphics and images quickly. In this paper, the design and implementation of 64 bit stream core operation unit are completed. The main work and innovations are as follows: 1. For integer operation unit, the addition / subtraction unit and multiplication unit are designed by taking full advantage of the narrow bit width of graphics and image processing data. These two units share leading zero logic with floating-point operations to deal with different bit widths flexibly, thus effectively utilizing resources and reducing computational delays. The design of comparison unit, shift unit and division unit in integer operation unit and the implementation of VHDL code are also completed. 2. For the floating-point operation unit, the floating-point addition / subtraction unit, the floating-point multiplication unit, the floating-point / integer conversion unit, the floating-point division unit, the floating-point square unit are designed and implemented, and the floating-point addition / subtraction is realized. Floating-point multiplication and floating-point / integer conversion are pipelined to improve the processing power of floating-point operation components. 3. The system verification platform of 64 bit stream core is designed by using the ISE12.1 development software of Xilinx Company. Test incentives are added to each unit to verify their functional correctness, and the correctness of pipelining processing is verified by executing multiple floating-point instructions. The verification results show that the design of the computing unit realizes the operation required by the processor and can run normally in the whole stream core system. Through the automatic synthesis of the software, the related performance parameters of the operation parts are obtained.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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