本文選題：LTE + PCI��； 參考：《武漢理工大學(xué)》2013年碩士論文

【摘要】：隨著通信技術(shù)的迅速發(fā)展,LTE應(yīng)運(yùn)而生,LTE系統(tǒng)具有網(wǎng)絡(luò)時(shí)延減少、更高的用戶數(shù)據(jù)速率、系統(tǒng)容量和覆蓋的改善的優(yōu)點(diǎn),但缺點(diǎn)也明顯：對(duì)帶寬的要求,對(duì)傳輸速率的要求等都使得系統(tǒng)更復(fù)雜。傳統(tǒng)的PCI,PCI_X等總線,因其性能無法達(dá)到系統(tǒng)的傳輸要求,正逐步淘汰,PCIe總線作為新一代的總線標(biāo)準(zhǔn),它具有數(shù)據(jù)傳輸速率高,可更好地支持未來高端顯卡等優(yōu)點(diǎn),在LTE系統(tǒng)的物理層中,設(shè)計(jì)基于PCIe總線DMA傳輸方式的數(shù)據(jù)通道平臺(tái)可有效進(jìn)行數(shù)據(jù)傳輸,減少了數(shù)據(jù)傳輸?shù)钠款i。并且PCIe總線具有良好的可擴(kuò)展性,可通過對(duì)系統(tǒng)升級(jí)來實(shí)現(xiàn)更高數(shù)據(jù)傳輸速率的要求。 本文設(shè)計(jì)的基于FPGA的PCIe總線DMA平臺(tái)系統(tǒng)的設(shè)計(jì)有很重要的實(shí)際意義,它充分利用了PCIE總線的眾多優(yōu)點(diǎn),解決了LTE系統(tǒng)中分布式基站的數(shù)據(jù)傳輸問題,為整個(gè)系統(tǒng)的實(shí)現(xiàn)打下了良好基礎(chǔ)。 本文的研究內(nèi)容包含以下三部分： 首先,深入研究了PCIe總線協(xié)議,剖析PCIe協(xié)議標(biāo)準(zhǔn)中三個(gè)層面的不同分工,在不同層面的數(shù)據(jù)傳送包的不同格式下的不同功能�？v觀LTE的發(fā)展?fàn)顩r,PCIe總線技術(shù)必成為主流。 其次,在深入研究了PCIe協(xié)議的基礎(chǔ)上,利用Xilinx公司的PCIe IP Core生成了系統(tǒng)所需的PCIe總線下的Endpoint模塊,在Endpoint模塊基礎(chǔ)上,設(shè)計(jì)DMA模塊,并針對(duì)本項(xiàng)目的要求設(shè)計(jì)接口模塊。 最后,編寫測(cè)試模塊,在Modelsim中對(duì)PCIe-DMA進(jìn)行聯(lián)合仿真,驗(yàn)證功能正確后,在ISE環(huán)境中進(jìn)行板上調(diào)試。 通過實(shí)際板卡測(cè)試,系統(tǒng)的DMA傳輸速度可穩(wěn)定達(dá)到2Gbps,沒有丟幀和誤碼現(xiàn)象,系統(tǒng)能夠穩(wěn)定運(yùn)行,能達(dá)到LTE系統(tǒng)中分布式基站中傳輸功能模塊的設(shè)計(jì)要求。 本文的創(chuàng)新點(diǎn)是虛擬FIFO的設(shè)計(jì),虛擬FIFO提供時(shí)鐘域的交叉,可存儲(chǔ)和轉(zhuǎn)發(fā)大的數(shù)據(jù)包,解決了DDR3SDRAM直接讀取寫入低效率的問題。采用了虛擬FIFO使需要讀取和寫入的數(shù)據(jù)包在此重新打包,可大大的提高傳輸效率,并且FIFO與memory controller直接相連,可忽略memory controller的反應(yīng)時(shí)間。
[Abstract]:With the rapid development of communication technology, LTE system has the advantages of reduced network delay, higher user data rate, improved system capacity and coverage. The requirement of transmission rate makes the system more complicated. Because the traditional PCI / PCIX bus can not meet the transmission requirements of the system, PCIe bus is being phased out as a new generation bus standard. It has the advantages of high data transmission rate and can better support the future high-end graphics card. In the physical layer of LTE system, the design of data channel platform based on PCIe bus DMA transmission mode can effectively carry out data transmission and reduce the bottleneck of data transmission. Moreover, PCIe bus has good expansibility and can achieve higher data transmission rate by upgrading the system. The design of PCIe bus DMA platform system based on FPGA in this paper is of great practical significance. It makes full use of the advantages of PCIE bus and solves the data transmission problem of distributed base station in LTE system. It lays a good foundation for the realization of the whole system. The research content of this paper includes the following three parts: Firstly, the PCIe bus protocol is deeply studied, the different division of labor in three layers of PCIe protocol standard is analyzed, and the different functions under different formats of data transfer packets at different levels are analyzed. Throughout the development of LTE, PCIe bus technology will become the mainstream. Secondly, based on the research of PCIe protocol, the Endpoint module based on PCIe bus is generated by the PCIe IP Core of Xilinx Company. The DMA module is designed on the basis of Endpoint module, and the interface module is designed according to the requirements of this project. Finally, the test module is written and the PCIe-DMA is simulated in Modelsim. After the function is correct, the test module is debugged in the ISE environment. Through the actual card test, the DMA transmission speed of the system can reach 2Gbps. there is no frame loss and error code phenomenon. The system can run stably and can meet the design requirements of the transmission function module in the distributed base station in the LTE system. The innovation of this paper is the design of virtual FIFO. Virtual FIFO provides the crossover of clock domain, can store and forward large packets, and solves the problem of low efficiency of DDR3SDRAM direct reading and writing. The virtual FIFO is used to repackage the data packets that need to be read and written, which can greatly improve the transmission efficiency, and the FIFO is directly connected with memory controller, and the memory controller reaction time can be ignored.
【學(xué)位授予單位】：武漢理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP336;TN929.5

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