本文選題：自適應(yīng)光學(xué) + 波前處理器��； 參考：《中國(guó)科學(xué)院研究生院（西安光學(xué)精密機(jī)械研究所）》2013年碩士論文

【摘要】：自適應(yīng)光學(xué)系統(tǒng)能有效克服大氣湍流帶來(lái)的波前誤差。然而，大氣變化的隨機(jī)性和瞬時(shí)性給自適應(yīng)光學(xué)系統(tǒng)的設(shè)計(jì)帶來(lái)了很大的困難，其中波前處理必須完成的大量實(shí)時(shí)運(yùn)算是一個(gè)難以克服的問(wèn)題。當(dāng)前波前處理器大多采用DSP（數(shù)字信號(hào)處理器）來(lái)實(shí)現(xiàn)波前處理運(yùn)算，DSP處理能賦予系統(tǒng)高精度和高靈活性；但是傳統(tǒng)DSP運(yùn)算速度制約了波前處理器的性能，給系統(tǒng)帶來(lái)了較大時(shí)延。 本文研究了波前處理器需要完成的波前斜率計(jì)算，波前復(fù)原和控制運(yùn)算等任務(wù)，，對(duì)Zernike模式法的各階有效性進(jìn)行了仿真，并且得出波前處理器的運(yùn)算量。結(jié)合波前處理器算法流程和運(yùn)算量需求，提出了矩陣分割，任務(wù)間流水線處理、子孔徑行與子孔徑內(nèi)并行計(jì)算的并行處理策略；在此理論基礎(chǔ)上本文設(shè)計(jì)了以FPGA和四個(gè)TMS320C6678為處理核心的并行波前處理平臺(tái)的軟件和硬件實(shí)現(xiàn)方案；該平臺(tái)的理論峰值處理速度達(dá)到每秒1280GMAC，系統(tǒng)時(shí)延約為30us，大大提升了波前處理器的性能。 結(jié)合平臺(tái)設(shè)計(jì)方案，本文對(duì)高性能波前處理平臺(tái)進(jìn)行了硬件設(shè)計(jì)。該平臺(tái)采用TI高性能8核DSP TMS320C6678為運(yùn)算單元，四個(gè)TMS320C6678組成一個(gè)流水線運(yùn)算陣列。硬件設(shè)計(jì)中本文采用分立結(jié)構(gòu)實(shí)現(xiàn)系統(tǒng)電源設(shè)計(jì)，通過(guò)監(jiān)控芯片完成上電順序控制；同時(shí)設(shè)計(jì)了豐富的內(nèi)外部高速接口和存儲(chǔ)空間；為了滿(mǎn)足多種圖像格式輸入的需要，另設(shè)計(jì)了寬度足夠的自定義通用圖像處理接口；文章最后對(duì)硬件平臺(tái)做了PCB設(shè)計(jì)和信號(hào)完整性分析，并對(duì)關(guān)鍵信號(hào)進(jìn)行仿真，驗(yàn)證了硬件設(shè)計(jì)的有效性。
[Abstract]:The adaptive optical system can effectively overcome the wavefront error caused by atmospheric turbulence. However, the randomness and instantaneity of atmospheric changes bring great difficulties to the design of adaptive optical systems, among which a large number of real-time operations that must be completed in wavefront processing are difficult to overcome. At present, most wavefront processors use DSP (Digital signal processor) to implement wavefront processing. DSPs can give high precision and high flexibility to the system, but traditional DSP speed restricts the performance of wavefront processor. It brings great delay to the system. In this paper, we study the tasks of wave front slope calculation, wave front recovery and control operation, and simulate the efficiency of Zernike mode method, and get the computation amount of wavefront processor. Considering the flow of wavefront processor algorithm and the requirement of computation, the parallel processing strategy of matrix partition, inter-task pipeline processing, parallel computation of sub-aperture line and sub-aperture is proposed. On the basis of this theory, the software and hardware implementation of parallel wavefront processing platform based on FPGA and four TMS320C6678 are designed. The theoretical peak processing speed of the platform reaches 1280GMAC / s and the system delay is about 30us. which greatly improves the performance of the wavefront processor. Combined with the platform design, this paper designs the hardware of the high performance wavefront processing platform. The platform uses TI high-performance 8 core DSP TMS320C6678 as computing unit and four TMS320C6678 to form a pipelined operation array. In the hardware design, the system power supply is designed with discrete structure, and the power supply sequence is controlled by the monitoring chip. At the same time, the rich internal and external high-speed interface and storage space are designed. In order to meet the needs of the input of various image formats, At last, the PCB design and signal integrity analysis of the hardware platform are done, and the key signals are simulated to verify the validity of the hardware design.
【學(xué)位授予單位】：中國(guó)科學(xué)院研究生院（西安光學(xué)精密機(jī)械研究所）
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類(lèi)號(hào)】：TP332

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