發(fā)布時(shí)間：2018-04-29 20:17

  本文選題：PCI + Express　； 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：機(jī)架式背板系統(tǒng)由于其在性能上的高容量交換能力和卓越的穩(wěn)定性成為復(fù)雜電子系統(tǒng)的主流構(gòu)架，，是當(dāng)今電信交換設(shè)備、高性能計(jì)算機(jī)等大型數(shù)字系統(tǒng)設(shè)計(jì)實(shí)現(xiàn)的基礎(chǔ)。PCI Express作為第三代I/O總線技術(shù)的典型代表，以其通道數(shù)多、帶寬高、兼容性好等性能受到業(yè)界的廣泛應(yīng)用與支持。但也正是因?yàn)镻CI Express高速率、高帶寬，尤其PCI Express3.0的傳輸速率達(dá)8Gbps，給電子系統(tǒng)設(shè)計(jì)師帶來(lái)了跨背板傳輸?shù)脑O(shè)計(jì)難題，即如何能有效地減小或者避免高速信號(hào)經(jīng)過(guò)長(zhǎng)距離傳輸所發(fā)生的諸如信號(hào)反射/衰減、介質(zhì)損耗、抖動(dòng)及碼間干擾等信號(hào)完整性（SI）問(wèn)題。 本文結(jié)合工程實(shí)際需求，搭建了基于背板的實(shí)驗(yàn)系統(tǒng)，針對(duì)PCI Express的傳輸鏈路進(jìn)行建模、設(shè)計(jì)和SI仿真，并對(duì)仿真結(jié)果進(jìn)行詳細(xì)地分析與研究。主要研究?jī)?nèi)容和成果包括以下幾個(gè)方面： 針對(duì)第三代I/O總線技術(shù)的發(fā)展，深入剖析了PCI Express的總線結(jié)構(gòu)與協(xié)議，重點(diǎn)研究分析了PCI Express3.0各協(xié)議層的特點(diǎn)、編碼方式，為后續(xù)PCI Express鏈路設(shè)計(jì)與SI仿真打下基礎(chǔ)。 針對(duì)高速PCB設(shè)計(jì)技術(shù)展開(kāi)研究，對(duì)高速傳輸鏈路中的各關(guān)鍵要素（包括疊層、板材、過(guò)孔、連接器等）逐一進(jìn)行分析、設(shè)計(jì)和SI仿真，尤其是分析了各個(gè)要素對(duì)高速信號(hào)傳輸?shù)挠绊懀⒃诜治龇抡婊A(chǔ)上對(duì)關(guān)鍵要素的參數(shù)進(jìn)行設(shè)計(jì)優(yōu)化，為后續(xù)實(shí)際工程設(shè)計(jì)做出了有益的嘗試。 針對(duì)本課題的設(shè)計(jì)目標(biāo)，分析了多種機(jī)架式背板系統(tǒng)的結(jié)構(gòu)及其特點(diǎn)，設(shè)計(jì)搭建了基于平行背板結(jié)構(gòu)的實(shí)驗(yàn)系統(tǒng)。根據(jù)實(shí)驗(yàn)系統(tǒng)的互連模式，構(gòu)建了跨背板的PCI Express高速信號(hào)傳輸鏈路模型。 針對(duì)工程設(shè)計(jì)的實(shí)際需求，運(yùn)用實(shí)驗(yàn)系統(tǒng)的高速信號(hào)傳輸鏈路模型，開(kāi)展了對(duì)不同速率（5Gbps和8Gbps）條件下多種板材（FR4和N4000-13SI）、多種傳輸距離（55cm、80cm和100cm）的SI仿真分析。通過(guò)對(duì)PCI Express2.0與PCI Express3.0兩種速率信號(hào)的跨背板傳輸進(jìn)行全面仿真與分析，得出工程設(shè)計(jì)的可傳輸?shù)脑O(shè)計(jì)距離。另外，為進(jìn)一步改善背板信號(hào)的傳輸質(zhì)量，提出了可在傳輸鏈路中增加中繼芯片來(lái)增加背板的傳輸距離的設(shè)計(jì)方法，并進(jìn)行了具有中繼芯片的鏈路仿真分析。最后，本文針對(duì)未來(lái)所面臨的14Gbps速率的背板設(shè)計(jì)進(jìn)行仿真與討論。
[Abstract]:Because of its high capacity and excellent stability, the frame backplane system has become the mainstream framework of complex electronic systems, and it is the telecommunication switching equipment nowadays. As a typical representative of the third generation of I / O bus technology, the design and implementation of large digital systems such as high-performance computers have been widely used and supported by the industry for its many channels, high bandwidth and good compatibility. But it is also because of the high speed and bandwidth of PCI Express, especially the 8Gbpss transmission rate of PCI Express3.0, which brings the electronic system designers the design problem of trans-backplane transmission. That is, how to effectively reduce or avoid the signal integrity problems such as signal reflection / attenuation, dielectric loss, jitter and inter-symbol interference (ISI) caused by long distance transmission of high speed signals. In this paper, an experimental system based on backplane is built to model, design and simulate the transmission link of PCI Express. The simulation results are analyzed and studied in detail. The main research contents and results include the following aspects: In view of the development of the third generation I / O bus technology, the bus structure and protocol of PCI Express are deeply analyzed, and the characteristics and coding methods of each protocol layer of PCI Express3.0 are emphatically studied, which lays a foundation for the design and SI simulation of subsequent PCI Express links. Based on the research of high speed PCB design technology, the key elements of high speed transmission link (including stack, plate, hole, connector, etc.) are analyzed one by one, and the design and SI simulation are carried out. In particular, the influence of various factors on high-speed signal transmission is analyzed, and the parameters of key elements are designed and optimized on the basis of analysis and simulation, which makes a useful attempt for the subsequent practical engineering design. Aiming at the design goal of this paper, the structure and characteristics of various machine frame backplane systems are analyzed, and the experimental system based on parallel backplane structure is designed and built. According to the interconnection mode of the experimental system, the PCI Express high-speed signal transmission link model across the backplane is constructed. In order to meet the practical requirements of engineering design, the SI simulation analysis of FR4 and N4000-13SISi, multiple transmission distances (55cm-1, 80cm and 100cm) under different rates (5Gbps and 8Gbpss) is carried out by using the high-speed signal transmission link model of the experimental system. Based on the simulation and analysis of the transmission of PCI Express2.0 and PCI Express3.0 signals across the backplane, the transmissible design distance of the engineering design is obtained. In addition, in order to further improve the transmission quality of backplane signal, a design method is proposed to increase the transmission distance of backplane by adding the relay chip to the transmission link, and the link simulation analysis with the relay chip is carried out. Finally, this paper simulates and discusses the design of 14Gbps rate backplane in the future.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP336

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