本文選題：MIPS + 微處理器��； 參考：《河北工業(yè)大學》2012年碩士論文

【摘要】：基于RISC架構(gòu)的MIPS指令兼容處理器是通用高性能處理器的一種。其架構(gòu)簡潔，運行效率高，在高性能計算，嵌入式處理，多媒體應(yīng)用等各個領(lǐng)域得到了廣泛應(yīng)用�；贔PGA的微處理器設(shè)計具有易于調(diào)試，便于集成的特點。在片上系統(tǒng)設(shè)計方法日趨流行的趨勢下，掌握一套復(fù)雜的微處理器設(shè)計技術(shù)十分必要。 論文首先概述了MIPS指令集的重要特征，為討論微處理器的具體設(shè)計奠定基礎(chǔ)。本設(shè)計實現(xiàn)了一個具有標準的32位5級流水線架構(gòu)的MIPS指令兼容CPU系統(tǒng)。具備常用的五十余條指令，解決了大部分數(shù)據(jù)相關(guān)，結(jié)構(gòu)相關(guān)，乘除法的流水化處理等問題。 文章的主體部分首先詳細描述了處理器各個獨立功能模塊的設(shè)計，為后續(xù)的整體設(shè)計實現(xiàn)提供邏輯功能支持。隨后按照指令執(zhí)行過程中需經(jīng)歷的五個階段，詳細描述了微處理器中各階段的邏輯設(shè)計。為了提高微處理器的工作效率，在微處理器設(shè)計實現(xiàn)的基礎(chǔ)上，深入研究了流水線技術(shù)及相關(guān)問題的解決方法，改進了傳統(tǒng)5級流水線結(jié)構(gòu)，并基本解決了數(shù)據(jù)相關(guān)、結(jié)構(gòu)相關(guān)和控制相關(guān)的問題。 在完成了微處理器的整體邏輯設(shè)計后，借助EDA工具對微處理器的工作狀態(tài)進行了軟件仿真，給出仿真結(jié)果，仿真波形驗證了微處理器的工作符合預(yù)想。最后用EDA工具對設(shè)計代碼綜合、實現(xiàn)，并下載到FPGA上，進行了簡單的硬件驗證。 通過驗證測試所得到的相關(guān)數(shù)據(jù)表明，論文所設(shè)計的32位微處理器滿足設(shè)計要求，其最高時鐘頻率達到了12.376MHz。
[Abstract]:MIPS instruction compatible processor based on RISC architecture is a universal high performance processor. It has been widely used in many fields, such as high performance computing, embedded processing, multimedia application and so on. The design of microprocessor based on FPGA is easy to debug and easy to integrate. It is necessary to master a set of complex microprocessor design techniques under the trend of the increasing popularity of system design methods on a chip. Firstly, this paper summarizes the important features of MIPS instruction set, which lays a foundation for discussing the design of microprocessor. This design implements a standard 32-bit 5-stage pipeline MIPS instruction compatible CPU system. With more than 50 instructions in common use, the problems of data correlation, structural correlation and pipelining of multiplication and division are solved. In the main part of the paper, the design of each independent function module of processor is described in detail, which provides the logical function support for the following whole design. Then, according to the five stages of instruction execution, the logic design of each stage in microprocessor is described in detail. In order to improve the working efficiency of the microprocessor, based on the design and implementation of the microprocessor, the pipeline technology and the solution of related problems are studied in depth, the traditional 5-stage pipeline structure is improved, and the data correlation is basically solved. Structural and control-related issues. After the whole logic design of the microprocessor is completed, the software simulation of the working state of the microprocessor is carried out with the help of EDA tool, and the simulation results are given. The simulation waveform verifies that the work of the microprocessor is in accordance with the expectation. Finally, the design code synthesis, implementation, and download to FPGA with EDA tools, a simple hardware verification. The data obtained from the verification test show that the 32-bit microprocessor designed in this paper meets the design requirements, and its highest clock frequency reaches 12.376MHz.
【學位授予單位】：河北工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332

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