本文選題：FPGA驗(yàn)證 + 嵌入式處理器��； 參考：《上海交通大學(xué)》2014年碩士論文

【摘要】：隨著科技進(jìn)步與發(fā)展，嵌入式處理器的應(yīng)用日益廣泛，設(shè)計(jì)規(guī)模和復(fù)雜度也飛速增長。FPGA相關(guān)技術(shù)的快速發(fā)展，為嵌入式處理器的功能驗(yàn)證提供技術(shù)基礎(chǔ)。本文旨在完成一款高性能嵌入式處理器FPGA驗(yàn)證工作。 本文首先對相關(guān)內(nèi)容進(jìn)行研究，包括嵌入式處理器結(jié)構(gòu)、芯片設(shè)計(jì)流程、功能驗(yàn)證方法、FPGA驗(yàn)證關(guān)鍵步驟、FPGA結(jié)構(gòu)和資源等。然后，基于一款高性能CPU內(nèi)核，提出并實(shí)現(xiàn)一款嵌入式處理器系統(tǒng)的硬件設(shè)計(jì)。利用豐富的FPGA資源，設(shè)計(jì)一個(gè)結(jié)構(gòu)簡單、靈活通用的FPGA驗(yàn)證平臺。在代碼設(shè)計(jì)階段開始搭建驗(yàn)證的基本系統(tǒng)，提前開始FPGA驗(yàn)證和軟件開發(fā)，提高驗(yàn)證效率，增加驗(yàn)證可靠性和驗(yàn)證平臺利用率。 本文具體闡述了驗(yàn)證平臺的實(shí)現(xiàn)過程。首先分析需求選擇可行方案，，然后介紹代碼移植過程，最后闡述基本系統(tǒng)搭建過程。以CPU核和DDR3測試為例介紹具體驗(yàn)證過程。在驗(yàn)證過程中，采用提前建立FPGA原型庫、腳本批量調(diào)用和修改代碼、使用多種調(diào)試方法等，努力提高可重用性和自動(dòng)化程度，減少人為錯(cuò)誤、提高工作效率。采用“模塊級——系統(tǒng)級——應(yīng)用級”遞進(jìn)式驗(yàn)證步驟，運(yùn)行操作系統(tǒng)和測試程序，實(shí)現(xiàn)功能驗(yàn)證目標(biāo)。驗(yàn)證結(jié)果表明驗(yàn)證平臺合理可靠、靈活通用，驗(yàn)證效率高。最后，對主要工作進(jìn)行總結(jié)。
[Abstract]:With the progress and development of science and technology, embedded processors are increasingly widely used, and the design scale and complexity are also growing rapidly. The rapid development of FPGA related technologies provides a technical basis for the functional verification of embedded processors. The purpose of this paper is to complete the FPGA verification of a high performance embedded processor. At first, this paper studies the related contents, including embedded processor structure, chip design flow, function verification method, FPGA verification key steps, FPGA structure and resources, and so on. Then, based on a high performance CPU kernel, the hardware design of an embedded processor system is proposed and implemented. Using abundant FPGA resources, a simple and flexible FPGA verification platform is designed. At the stage of code design, the basic system of verification is built, FPGA verification and software development are started in advance, the efficiency of verification is improved, the reliability of verification and the utilization rate of verification platform are increased. This paper describes the implementation process of the verification platform. This paper first analyzes the requirements of selecting feasible solutions, then introduces the process of code transplantation, and finally describes the process of building the basic system. Taking CPU kernel and DDR3 test as examples, the concrete verification process is introduced. In the process of verification, FPGA prototype library is built ahead of time, script batch calls and modifies code, and many debugging methods are used to improve reusability and automation, reduce human error and improve work efficiency. The function verification goal is realized by using the progressive verification step of "module level-system level-application level", running the operating system and testing program. The verification results show that the verification platform is reasonable and reliable, flexible and universal, and has high verification efficiency. Finally, the main work is summarized.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP332

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本文編號：1820966