本文選題：DSP + IP核　； 參考：《國防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：隨著計算機技術(shù)和集成電路工藝的發(fā)展,微處理器的主頻越來越高,中央處理單元(CPU)計算能力的增長遠遠超過了存儲器性能的增加。CPU與存儲器之間性能差異的“存儲墻”問題已成為制約微處理器整體性能進一步提高的瓶頸。而在面向無線通信、圖像處理等流媒體應(yīng)用的向量處理器中,存儲墻的問題尤為嚴重。如何為向量處理器中的向量處理單元提供更為靈活和高效的向量數(shù)據(jù)訪存方式,發(fā)揮向量處理單元的計算能力,擴展向量處理器的應(yīng)用范圍及其在片上系統(tǒng)(System-on-Chip,SoC)上的集成是設(shè)計高性能向量處理器、提高其市場競爭力的關(guān)鍵。 YHFT-Matrix是國防科學(xué)技術(shù)大學(xué)自主研發(fā)的一款面向軟件無線電(Software Defined Radio, SDR)應(yīng)用的高性能向量數(shù)字信號處理器內(nèi)核；本文針對YHFT-Matrix內(nèi)核體系結(jié)構(gòu)及其無線通信相關(guān)算法的訪存特點,對其片上大容量向量存儲器(Vector Memory,VM)及其參數(shù)化IP (Intellectual Property)設(shè)計展開研究,針對向量訪存的效率和靈活性面臨的問題,提出了基于SIMD結(jié)構(gòu)的向量訪存指令集和向量存儲器總體方案,設(shè)計實現(xiàn)了支持多寬度SIMD向量數(shù)據(jù)條件訪問和非對齊訪問的VM,包括VM中的譯碼、向量地址計算、向量訪存仲裁、數(shù)據(jù)寫回對齊等訪存流水線功能模塊的邏輯結(jié)構(gòu)。在此基礎(chǔ)上,根據(jù)YHFT-Matrix IP軟核的應(yīng)用多樣性設(shè)計需求,提取VM的設(shè)計參數(shù),實現(xiàn)了SIMD寬度和存儲體容量可配置的參數(shù)化IP設(shè)計,其中VM IP的SIMD寬度N可設(shè)計為2、4、8或16四種配置,向量存儲體容量設(shè)計為16KB或64KB兩種配置。 最后對VM IP軟核進行了模塊級、系統(tǒng)級功能驗證和邏輯綜合。實驗結(jié)果表明,在各種設(shè)計參數(shù)配置情況下VM IP功能正確,滿足設(shè)計要求；在TMSC的45nm工藝下,達到了700MH的工作頻率,最大配置下能同時為向量處理單元(VPU)提供717Gbps的向量訪存帶寬、357Gbps的DMA數(shù)據(jù)訪問帶寬和45Gbps的標量訪存帶寬,很好滿足了向量存儲器運算部件對數(shù)據(jù)吞吐率和訪存性能的較高要求。
[Abstract]:With the development of computer technology and integrated circuit technology, the main frequency of microprocessor becomes higher and higher. The increase of computing power of central processing unit (CPU) greatly exceeds the increase of memory performance. The problem of "memory wall" which restricts the performance difference between CPU and memory has become a bottleneck restricting the further improvement of the overall performance of microprocessors. In vector processors for streaming media applications such as wireless communication and image processing, the problem of storage wall is especially serious. How to provide a more flexible and efficient way to access and store vector data for vector processing units in vector processors, so as to give full play to the computing power of vector processing units, The application scope of extended vector processor and its integration on on-chip system (System-on-ChipPU SoC) are the key to design high performance vector processor and improve its market competitiveness. YHFT-Matrix is a high-performance vector digital signal processor kernel developed by the University of National Defense Science and Technology, which is oriented to the application of Software Radio Software Defined Radio (SDRs). This paper aims at the memory access characteristics of the YHFT-Matrix kernel architecture and its wireless communication algorithms. This paper studies the design of VMs and their parameterized IP intellectual property. Aiming at the problems of the efficiency and flexibility of vector memory access, a general scheme of vector access instruction set and VRAM based on SIMD structure is proposed. This paper designs and implements the logic structure of VMs which support multi-width SIMD vector data conditional access and unaligned access, including VM decoding, vector address calculation, vector memory access arbitration, data write-back alignment and other memory access pipeline function modules. On this basis, according to the diversity design requirements of YHFT-Matrix IP soft core, the design parameters of VM are extracted, and the parameterized IP design with configurable SIMD width and storage capacity is realized. The SIMD width N of VM IP can be designed as 2 / 4 / 8 or 16 configurations. Vector storage capacity is designed for 16KB or 64KB configurations. Finally, the module level, system level function verification and logic synthesis of VM IP soft core are carried out. The experimental results show that the VM IP functions are correct and meet the design requirements under various design parameter configurations, and the working frequency of 700MH is achieved under the 45nm process of TMSC. Under the maximum configuration, the vector access bandwidth of 717Gbps and the scalar access bandwidth of 45Gbps can be provided to the vector processing unit (VPUU) at 357Gbps at the same time, which meets the higher requirements of the VRAM operation unit for data throughput and memory access performance.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333

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