本文選題：高性能CPU + 鎖相環(huán)　； 參考：《國防科學(xué)技術(shù)大學(xué)》2013年博士論文

【摘要】：半導(dǎo)體工藝進入納米時代，在工藝的推動下CPU技術(shù)取得了長足的進步，特別是高性能CPU的工作主頻得到了大幅度的提升，以IBM Power系列為代表的先進微處理器的工作主頻已經(jīng)超過了5GHz。高工作主頻對時鐘系統(tǒng)的穩(wěn)定性提出了很高的要求，時鐘系統(tǒng)任何微小抖動就可能導(dǎo)致CPU的性能下降或者功能異常。鎖相環(huán)作為首選的時鐘發(fā)生器無可取代地成為了幾乎所有CPU芯片時鐘系統(tǒng)的原點。與工作在其它場合的鎖相環(huán)不同，高性能CPU內(nèi)部成分復(fù)雜的電源噪聲、劇烈波動的芯片溫度以及鎖相環(huán)內(nèi)部件的電路特性都會影響鎖相環(huán)的抖動性能，從而成為限制CPU性能的一個重要因素。因此，站在CPU的視角，全面地看待鎖相環(huán)的抖動問題，研究以面向高性能CPU應(yīng)用為背景的鎖相環(huán)低抖動技術(shù)成為了高性能CPU研究的先決條件之一。 從高性能CPU對鎖相環(huán)的特性需求出發(fā)，本文緊密圍繞鎖相環(huán)的抖動問題，對由CPU內(nèi)電源噪聲、環(huán)境溫度這類“外在”因素，以及環(huán)路內(nèi)壓控振蕩器結(jié)構(gòu)這類“內(nèi)在”因素導(dǎo)致的鎖相環(huán)抖動問題分別進行了機理分析，并針對性地提出了解決方案。本文的主要創(chuàng)新點可歸納為以下五個方面： 1.從高性能CPU的視角審視鎖相環(huán)的抖動問題，結(jié)合CPU的特點分析產(chǎn)生抖動的外在和內(nèi)在因素，確立鎖相環(huán)低抖動設(shè)計的目標和著力點。 針對為高性能CPU提供高頻穩(wěn)定時鐘這一應(yīng)用目標，本文跳出鎖相環(huán)環(huán)路這一既定框架，從更廣闊的視角審視鎖相環(huán)的抖動問題。以環(huán)路內(nèi)外結(jié)合的方式，從CPU的角度分析了高性能CPU固有的電氣、溫度因素對鎖相環(huán)抖動特性的影響，提煉出時鐘抖動與電源、時鐘抖動與偏置、時鐘抖動與電路結(jié)構(gòu)之間的內(nèi)在聯(lián)系，確定低抖動研究的方向和目標。 2.提出了電流控制模式的低壓差穩(wěn)壓器（LDO）模型，并采用提出的八邊形網(wǎng)格狀大尺寸功率晶體管版圖結(jié)構(gòu)，實現(xiàn)了一種內(nèi)嵌式采用電流控制型LDO鎖相環(huán)供電電路。 針對高性能CPU內(nèi)部復(fù)雜的電源噪聲，依據(jù)“本地產(chǎn)生，本地使用”的原則，本文提出了內(nèi)嵌LDO的鎖相環(huán)供電結(jié)構(gòu)框架，最大限度地降低外界噪聲耦合進入鎖相環(huán)電源網(wǎng)絡(luò)的可能性。同時，本文還提出了基于電流環(huán)路控制技術(shù)的流控型LDO結(jié)構(gòu)——CCL-LDO，在CCL-LDO環(huán)路中應(yīng)用電流控制技術(shù)，發(fā)揮電流信號響應(yīng)速度快的特點，大幅度地提高了LDO電路的瞬態(tài)響應(yīng)能力，在面對鎖相環(huán)這類處于振蕩狀態(tài)的負載時能有效穩(wěn)定供電電壓、降低紋波，從“外因”上降低鎖相環(huán)輸出發(fā)生抖動的可能性。CCL-LDO分別作用于電荷泵和壓控振蕩器的實驗結(jié)果表明，其對電荷泵和壓控振蕩器相位噪聲的抑制可達-40dB～-60dB，能大幅度地降低鎖相環(huán)輸出時鐘的抖動。 此外，大尺寸功率晶體管也是影響LDO性能的一個重要因素，本文提出了大尺寸功率晶體管的八邊形網(wǎng)格狀版圖實現(xiàn)技術(shù)，有效地抑制了大尺寸功率晶體管的襯底偏壓累積，確保了大尺寸功率晶體管閾值電壓的穩(wěn)定。 3.針對CPU芯片特點，提出了兩種高溫度穩(wěn)定性的帶隙基準電路，降低了偏置信號溫度漂移對鎖相環(huán)工作穩(wěn)定性的影響。 針對CPU在不同工作負載下溫度波動劇烈的問題，深入地研究了帶隙基準電壓/電流源電路偏置技術(shù)，發(fā)現(xiàn)并分析了帶隙基準核心電路中由PNP管“發(fā)射極-基極”電流通路的分流作用導(dǎo)致的溫度漂移現(xiàn)象，，提出了“發(fā)射極-基極”電流補償方案，利用不同材料的溫度特性實現(xiàn)了電阻的溫度漂移補償，并在此基礎(chǔ)上分別實現(xiàn)了兩款高溫度穩(wěn)定性的帶隙基準電壓/電流源電路。分析表明，基于帶隙基準的偏置信號溫度穩(wěn)定性達到1ppm/℃級別，確保了鎖相環(huán)環(huán)路的直流工作狀態(tài)的穩(wěn)定。 4.深入分析壓控振蕩器（VCO）工作過程中的非平衡因素，揭示并分析了壓控振蕩器的“本征抖動”現(xiàn)象，并針對性地提出了雙環(huán)互鎖/多環(huán)前饋自交叉式單端VCO結(jié)構(gòu)。 通過對壓控振蕩器振蕩機理的分析，揭示了單端壓控振蕩器非對稱結(jié)構(gòu)導(dǎo)致的“本征抖動”現(xiàn)象，分析了振蕩過程中正負半周期內(nèi)工作電流非平衡這一產(chǎn)生本征抖動的根本機理。針對本征抖動問題，提出了雙環(huán)互鎖壓控振蕩器結(jié)構(gòu)，并在此基礎(chǔ)上進一步地衍生出多環(huán)前饋自交叉技術(shù)，實現(xiàn)了中心對稱的“偶數(shù)級單端壓控振蕩器”，平衡了壓控振蕩器的工作電流，對“本征抖動”的抑制效果大于80%，并且具有極佳的線性度。 5.針對電源噪聲和控制電壓噪聲導(dǎo)致的VCO抖動，提出并實現(xiàn)了內(nèi)嵌有源LC濾波器的壓控振蕩器技術(shù)。 從VCO的組成結(jié)構(gòu)上看，來自電源和控制電壓的噪聲均可導(dǎo)致輸出抖動，本文深入地分析了這兩類噪聲的傳播方式和機理，提出了在噪聲傳播路徑公共點進行噪聲濾波的方法，并結(jié)合CPU工藝的特點，提出了內(nèi)嵌有源LC濾波的壓控振蕩器技術(shù)，有效地衰減了進入環(huán)形振蕩器的噪聲，鎖相環(huán)的抖動降低超過-30dB。 基于上述技術(shù)，本文設(shè)計了一款基于40nm工藝的低抖動鎖相環(huán)電路，分析結(jié)果表明，對比簡單結(jié)構(gòu)的鎖相環(huán)電路，該鎖相環(huán)電氣原因?qū)е碌亩秳拥木礁到档土?6%，溫度因素導(dǎo)致的抖動的均方根值下降了58%。
[Abstract]:The semiconductor technology has entered the nanoscale era. The CPU technology has made great progress in the process of technology, especially the main frequency of the high performance CPU has been greatly improved. The main frequency of the advanced microprocessor, represented by the IBM Power series, has exceeded the 5GHz. high working master frequency to the stability of the clock system. Any tiny jitter in the clock system may lead to CPU performance degradation or function abnormality. Phase locked loop, as the preferred clock generator, becomes the origin of almost all CPU chip clock systems. Unlike the phase locked loops working on other occasions, the complex power noise and volatile core of the high performance CPU inner components are complex. The chip temperature and the circuit characteristics of the components in the phase-locked loop will affect the jitter performance of the PLL, thus becoming an important factor restricting the performance of CPU. Therefore, from the perspective of CPU, the jitter of the PLL is viewed in a comprehensive way, and the low jitter technology based on the high performance CPU application is studied in the high performance CPU research. One of the prerequisites.
Based on the characteristic demand of high performance CPU for phase locked loop, this paper focuses on the jitter of phase-locked loop, and analyzes the mechanism of the phase-locked loop jitter caused by the "internal" factors such as the power noise in the CPU, the ambient temperature, and the internal factors such as the inner loop voltage controlled oscillator structure. The main innovations of this paper can be summed up in the following five aspects:
1. from the perspective of high performance CPU, we examine the jitter of PLL, combine the characteristics of CPU to analyze the external and internal factors of the jitter, and establish the target and focus of the low jitter design of the PLL.
In order to provide high frequency stable clock for high performance CPU, this paper jumps out the established framework of PLL loop to examine the jitter of PLL from a broader perspective. The effect of temperature factors on the jitter characteristics of phase locked loop is analyzed from the angle of CPU and the influence of temperature factors on the jitter characteristics of phase locked loop from the way of combining the loop inside and outside the loop. The relationship between clock jitter and power supply, clock jitter and offset, clock jitter and circuit structure is determined, and the direction and goal of low jitter research are determined.
2. a current control model of low voltage differential voltage regulator (LDO) is proposed, and a new type of LDO PLL power supply circuit with current controlled type is realized by using the proposed eight edge shaped grid like large size power transistor layout structure.
In view of the complex power noise inside the high performance CPU, according to the principle of "local generation and local use", this paper proposes a PLL power supply framework with embedded LDO to minimize the possibility of external noise coupling into the PLL power network. At the same time, the flow control LDO based on current loop control technology is also proposed. Structure - CCL-LDO, the application of current control technology in the CCL-LDO loop, which gives full play to the fast response of the current signal, greatly improves the transient response ability of the LDO circuit. It can effectively stabilize the power supply voltage, reduce the ripple and reduce the output of the PLL from the "external cause" in the face of the phase locked loop such as the oscillating state. The possibility of jitter effect on the experimental results of the charge pump and the voltage controlled oscillator show that the phase noise of the charge pump and the voltage controlled oscillator can be suppressed by -40dB to -60dB, which can greatly reduce the jitter of the output clock of the PLL.
In addition, large size power transistors are also an important factor affecting the performance of LDO. In this paper, a eight edge grid pattern realization technique for large size power transistors is proposed, which effectively inhibits the accumulation of bias voltage of large size power transistors and ensures the stability of the threshold voltage of large size power transistors.
3. according to the characteristics of CPU chip, two kinds of bandgap reference circuits with high temperature stability are proposed, which reduces the effect of bias signal temperature drift on the stability of PLL.
In view of the severe temperature fluctuation of CPU under different working loads, the bias technology of bandgap voltage / current source circuit is deeply studied. The temperature drift caused by the shunt action of the "emitter base" current path of the PNP tube is found and analyzed in the bandgap reference core circuit, and the "emitter base" current is proposed. The compensation scheme is used to compensate the temperature drift of the resistance by using the temperature characteristics of different materials. On this basis, two bandgap voltage / current source circuits with high temperature stability are realized. The analysis shows that the temperature stability of the bias signal based on the bandgap datum reaches the level of 1ppm/ C, which ensures the DC working form of the phase locked loop. The state is stable.
4. the nonequilibrium factors in the working process of the voltage controlled oscillator (VCO) are deeply analyzed, and the "eigenjitter" phenomenon of the VCO is revealed and analyzed, and the double ring interlocking / multi loop feedforward self crossing single end VCO structure is proposed.
By analyzing the oscillation mechanism of the voltage controlled oscillator, the phenomenon of "intrinsic jitter" caused by the asymmetric structure of a single terminal voltage controlled oscillator is revealed. The fundamental mechanism of the eigenjitter in the positive and negative half cycle of the oscillating process is analyzed, and the structure of the double ring interlocked voltage controlled oscillator is proposed. On this basis, the multi loop feed-forward self crossing technique is further derived, which realizes the centrally symmetric "even number single end voltage controlled oscillator", which balances the operating current of the VCO, and the suppression effect of the "eigenjitter" is greater than 80%, and has excellent linearity.
5. aiming at VCO jitter caused by power noise and voltage noise, a voltage controlled oscillator with embedded active LC filter is proposed and implemented.
From the structure of the VCO, the noise from the power supply and the control voltage can cause the output jitter. In this paper, the propagation mode and mechanism of the two kinds of noise are analyzed. The noise filtering method is proposed in the common point of the noise propagation path, and the voltage controlled oscillator with the active LC filter is proposed in combination with the characteristics of the CPU process. It effectively attenuates the noise entering the ring oscillator, and the jitter of the PLL is reduced by more than -30dB.
Based on the above technology, a low jitter PLL circuit based on 40nm technology is designed. The analysis results show that the root mean square value of the jitter of the phase locked loop is reduced by 66%, and the mean square root of the jitter caused by the temperature factor is reduced by 58%..

【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2013
【分類號】：TP332;TN911.8

【參考文獻】

相關(guān)期刊論文 前4條

1 周前能;王永生;來逢昌;;A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation[J];半導(dǎo)體學(xué)報;2009年04期

2 馬卓;譚曉強;謝倫國;郭陽;;A curvature calibrated bandgap reference with base-emitter current compensating in a 0.13μm CMOS process[J];半導(dǎo)體學(xué)報;2010年11期

3 馬卓;郭陽;段志奎;謝倫國;陳吉華;余金山;;A fast transient response low dropout regulator with current control methodology[J];半導(dǎo)體學(xué)報;2011年08期

4 李演明;來新泉;賈新章;曹玉;葉強;;具有快速瞬態(tài)響應(yīng)和低靜態(tài)電流的CMOS低漏失穩(wěn)壓器設(shè)計[J];電子學(xué)報;2009年05期

本文編號：1773019