發(fā)布時間：2018-03-25 11:31

  本文選題：片上總線　切入點：CPU卡　出處：《計算機(jī)應(yīng)用與軟件》2014年05期

【摘要】：針對CPU卡設(shè)計規(guī)模小以及設(shè)計時間和成本有限等特點,選擇合適的片上總線互聯(lián)結(jié)構(gòu),設(shè)計一套虛擬原型驗證平臺。介紹虛擬原型驗證平臺的原理,著重分析采用AHB-lite片上總線結(jié)構(gòu)能夠極大地減小CPU卡設(shè)計的復(fù)雜度。運用搭建的CPU卡虛擬原型驗證平臺,對CPU卡的架構(gòu)和自主設(shè)計的IP模塊進(jìn)行測試,并在實際的物理原型驗證平臺上對整個架構(gòu)進(jìn)行測試。測試結(jié)果表明設(shè)計的虛擬原型驗證平臺可以切實地減少設(shè)計的時間和成本。
[Abstract]:In view of the characteristics of small design scale and limited design time and cost of CPU card, a set of virtual prototype verification platform is designed by selecting appropriate on-chip bus interconnection structure, and the principle of virtual prototype verification platform is introduced. The complexity of CPU card design can be greatly reduced by using AHB-lite on-chip bus structure. Using the virtual prototype verification platform of CPU card, the architecture of CPU card and the independent design IP module are tested. The test results show that the virtual prototype verification platform can effectively reduce the design time and cost.
【作者單位】： 南通大學(xué)江蘇省專用集成電路設(shè)計重點實驗室;中國科學(xué)院半導(dǎo)體研究所;
【基金】：交通運輸部科技項目(2011-364-813060)
【分類號】：TP332

【參考文獻(xiàn)】

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1 馬秦生;曹陽;楊s，

本文編號：1662934