本文選題：靈敏放大器　切入點(diǎn)：高速　出處：《安徽大學(xué)》2012年碩士論文

【摘要】：靈敏放大器因?yàn)榫哂袡z測(cè)小擺幅信號(hào)并可以將其快速放大為全擺幅邏輯信號(hào)的功能,所以已經(jīng)被廣泛運(yùn)用于各種數(shù)字及模擬電路中,例如存儲(chǔ)器(SRAM、 DRAM、Flash)、A/D轉(zhuǎn)化器、數(shù)據(jù)接收器、片上收發(fā)器等。根據(jù)不同的應(yīng)用領(lǐng)域,其結(jié)構(gòu)略有不同,本文從提高SRAM存取速度的角度出發(fā),重點(diǎn)研究了SRAM系統(tǒng)中的關(guān)鍵模塊——靈敏放大器,在此基礎(chǔ)上設(shè)計(jì)出了一種新型結(jié)構(gòu)的高速靈敏放大器和提出了一種新型靈敏放大器失調(diào)電壓的減小技術(shù),并將該技術(shù)運(yùn)用于一款512words×32bits的高速SRAM設(shè)計(jì)中。 靈敏放大器的設(shè)計(jì)主要需要考慮失調(diào)、速度、功耗、面積和良率等指標(biāo),其中失調(diào)是其最重要的參數(shù)。隨著半導(dǎo)體工藝技術(shù)的不斷進(jìn)步,工藝誤差更容易導(dǎo)致器件的失配,由此更容易引起小擺幅輸入信號(hào)被靈敏放大器錯(cuò)誤放大,因此這對(duì)靈敏放大器的設(shè)計(jì)提出了更高的要求。 本文首先分析了新工藝下靈敏放大器的設(shè)計(jì)重點(diǎn)和難點(diǎn),然后分析了幾種常用結(jié)構(gòu)靈敏放大器的優(yōu)缺點(diǎn)。針對(duì)兩種常用結(jié)構(gòu)靈敏放大器存在的優(yōu)缺點(diǎn),本文提出了一種新型結(jié)構(gòu)的高速靈敏放大器,在SMIC65nm工藝下的仿真結(jié)果表明,對(duì)比結(jié)構(gòu)一及二型靈敏放大器,與新型結(jié)構(gòu)靈敏放大器連接的位線對(duì)形成相同差分電壓的延時(shí)最小,其延時(shí)最大可減小18.26%;在相同仿真條件下,放大300mV差分電壓,相比結(jié)構(gòu)一型靈敏放大器,新型結(jié)構(gòu)靈敏放大器速度可提高25.62%～50.38%,能耗可減小18.31%～27.72%；相比結(jié)構(gòu)二型靈敏放大器,新型結(jié)構(gòu)靈敏放大器速度可提高47.56%～58.72%,能耗可減小19.63%～44.98%。針對(duì)工藝進(jìn)步導(dǎo)致失調(diào)增大的情況,本文提出了一種用于降低靈敏放大器失調(diào)電壓,提高SRAM讀操作速度的技術(shù)。所提出的失調(diào)電壓減小方案在不需要任何面積補(bǔ)償?shù)那疤嵯卤隳艽蠓葴p小靈敏放大器的失調(diào),并提高SRAM的讀操作速度,通過(guò)仿真驗(yàn)證,當(dāng)使能信號(hào)電壓值減小至0.6V時(shí),兩種靈敏放大器失調(diào)電壓的標(biāo)準(zhǔn)偏差減小幅度分別達(dá)到31.23%和25.17%；最優(yōu)點(diǎn)時(shí),與StrongARM SA相連的單列存儲(chǔ)陣列總延時(shí)減小了14.98%,與Double-tail SA相連的單列存儲(chǔ)陣列總延時(shí)減小了22.26%；當(dāng)使能信號(hào)電壓值為0.6V、位線掛載1024個(gè)存儲(chǔ)單元時(shí),與StrongARM型靈敏放大器相連的單列存儲(chǔ)陣列總能耗減小了30.45%,與Double-tail SA相連的單列存儲(chǔ)陣列總能耗減小了29.47%。本文最后將所提出的失調(diào)減小技術(shù)應(yīng)用于一款容量為16Kb的SRAM中,前仿真結(jié)果Tcq的值介于226.1ps～644.3ps之間,后仿真結(jié)果介于644.1ps～1120.2ps之間,都小于1.25ns,完全達(dá)到項(xiàng)目指標(biāo)800MHz～1.25GHz的要求。
[Abstract]:Because of the sensitive amplifier detecting low swing signal and can be quickly enlarged to full swing signal logic function, so it has been widely used in a variety of digital and analog circuits, such as memory (SRAM, DRAM, Flash), A/D converter, data receiver, on-chip transceiver and so on. According to the different application area. Its structure is slightly different, in order to improve the access speed of SRAM point of view, focusing on the key modules of the SRAM system in the sense amplifier, based on the design of a new structure of high speed sensitive amplifier and puts forward a new sense amplifier offset voltage reduction technique, and will use the technology of high speed SRAM design in a 512words * 32bits.
The design of sensitive amplifier mainly need to consider the imbalance, speed, power, area and yield index, the imbalance is the most important parameter. With the development of semiconductor technology, process errors more easily lead to device mismatch, which is more likely to cause small amplitude error sensitive amplifier input signal is amplified, so put forward this is a higher demand for the sense amplifier design.
This paper first analyzes the key and difficulty of sense amplifier design under the new technology, and then analyzes the advantages and disadvantages of several common sense amplifiers. The advantages and disadvantages of two kinds of common sense amplifiers, this paper proposes a new structure of high speed sensitive amplifier, simulation results show that under the SMIC65nm process, and a comparative structure the two sense amplifier, and novel structure of sensitive amplifier connected bit line to form the same differential voltage delay, the maximum time delay can be decreased by 18.26%; in the same simulation conditions, 300mV differential voltage amplifier, a sense amplifier is compared with the structure, the new structure sensitive amplifier speed can be increased to 25.62% ~ 50.38%, the energy consumption can be reduced from 18.31% to 27.72%; compared with the structure of the two sense amplifier, structure sensitive amplifier speed can be increased from 47.56% to 58.72%, the energy consumption can be reduced from 19.63% to 44.98%. According to the technology progress result in disorders of the increase, this paper puts forward a method for reducing the sense amplifier offset voltage, improve the operating speed of the SRAM reading technology. The premise proposed offset voltage reduction scheme does not require any compensation in the area can greatly reduce the imbalance under the sensitive amplifier, and improve the read operation speed of SRAM through the simulation, when the enable signal voltage decreases to 0.6V, two standard deviation sensitive amplifier offset voltage is reduced by 31.23% and 25.17% respectively; the advantages, connected with the StrongARM SA single storage array total delay is reduced by 14.98%, the total delay is connected with the Double-tail SA single memory array is reduced 22.26%; when the enable signal voltage is 0.6V, the bit line mount 1024 storage units, the total energy consumption is connected with the StrongARM type sense amplifier single memory array is reduced by 30.45%, The total energy consumption is connected with the Double-tail SA single memory array is reduced by 29.47%. at the end of this paper, the proposed offset reduction technique applied to a capacity of 16Kb SRAM, the simulation results of Tcq values ranged from 226.1ps to 644.3ps, after the simulation results from 644.1ps to 1120.2ps, are less than 1.25ns, fully meet the project index 800MHz to the requirements of 1.25GHz.

【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333;TN722

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本文編號(hào)：1654690