本文選題：余數(shù)系統(tǒng)　切入點：無損動態(tài)擴展方法　出處：《電子科技大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：和傳統(tǒng)的使用硬件規(guī)模帶來的并行性的方式不同,RNS是一種使用并行的數(shù)值表征系統(tǒng)達(dá)到天然并行的性的方法。近些年來以RSA、ECC為代表的公鑰算法廣泛使用了 RNS架構(gòu)以提升加密的速度。隨著秘鑰長度的增加,對于RNS下算法單元尤其是模2~n-2~p -1下乘法單元的位寬和性能提出了更高的要求。另外后向轉(zhuǎn)換作為RNS架構(gòu)下的難點,一直是RNS架構(gòu)的性能瓶頸之一,{2~n-1、2~n+3、2~n+1、2~n-3}下快速后向轉(zhuǎn)換算法被提出后,由于模2~n+3下乘法單元的性能問題而少有應(yīng)用。本文結(jié)合余數(shù)系統(tǒng)在密碼學(xué)應(yīng)用和快速后向轉(zhuǎn)換等方向的最新進(jìn)展,針對相應(yīng)的特殊余數(shù)基下的算法單元進(jìn)行了深入的研究。通過對大量模2~n±1乘法器相關(guān)參考文獻(xiàn)進(jìn)行分類研究,對適合本文設(shè)計要求的架構(gòu)進(jìn)行了篩選。本文根據(jù)模修正在二進(jìn)制乘法器介入的部位不同將模乘法器分為四種類型,并按照數(shù)據(jù)流的執(zhí)行順序進(jìn)行了命名,分別為修正1型、修正2型、修正3型以及修正4型。按照本文的分類方式,選擇形式為2~n-2~p-1、2~n+3余數(shù)基下的算法單元做了如下工作:1.針對2~n -2~p -1類型動態(tài)范圍利用率較低的問題,使用現(xiàn)有文獻(xiàn)中的擴展方法,對模2~n-2~p-1加法運算的相關(guān)公式進(jìn)行推導(dǎo),降低了其約束條件并且將修正所需的判定項由A+B + T化簡為A + B。從而提出了一種適合2~n-2~p-1余數(shù)基下算法單元應(yīng)用的無損動態(tài)擴展方法。使用無損動態(tài)范圍擴展后的模2~n -2~p -1加法器和乘法器較同種結(jié)構(gòu)的算法單元在“面積X時延”效率上分別提高了 41.1%和12.3% 。2.提出了一種修正1型模2~n-2~p-1乘法器,利用模2~n-2~p-1的性質(zhì),將包含布斯編碼選擇項的部分積中可能出現(xiàn)的負(fù)數(shù)問題進(jìn)行修正。經(jīng)過公式推導(dǎo),將未修正部分積和修正項進(jìn)行合理的分離,使未修正部分積可以最大程度利用二進(jìn)制布斯編碼部分積生成的相關(guān)電路,最終得到了規(guī)整的部分積。這種結(jié)構(gòu)較傳統(tǒng)的通用型模乘法在平均時延和平均面積上分別減少了 49.1%和6.5%。3.針對修正3型提出了兩種不同結(jié)構(gòu)的模2~n-2~p-1乘法器,在布斯結(jié)構(gòu)中通過預(yù)先計算解決了將2~n位有符號補碼表示的部分積較難修正至n位的問題。進(jìn)而獲得了一個與(n,p)取值組合無關(guān)的統(tǒng)一結(jié)構(gòu)。在TDM結(jié)構(gòu)中首次將TDM算法引入到模乘法器的設(shè)計當(dāng)中,推導(dǎo)得到了一種較使用布斯編碼更為精簡的快速型結(jié)構(gòu)。這兩種模2~n -2~p -1乘法器在平均時延上較當(dāng)前的模2~n- 2~p-1乘法器最高可以降低9.7%。4.針對修正4型對2~n -2~p -1、2~n+3兩種余數(shù)基分別提出了兩種乘法器結(jié)構(gòu)。在模2~n -2~p -1乘法器中,其關(guān)鍵路徑上使用一級CSA代替了原來的一個p位二進(jìn)制進(jìn)位傳播加法器,縮短了關(guān)鍵路徑的時延。在模2~n+3乘法器,利用模2~n+3性質(zhì)在部分積進(jìn)行壓縮時產(chǎn)生“+9”和“-9”進(jìn)行抵消,節(jié)約了額外處理“-9”所需要的硬件資源。降低了關(guān)鍵路徑的時延。兩種結(jié)構(gòu)較當(dāng)前的同類型模乘法器在“面積×?xí)r延”效率上分別提高了 12.4%和9.0%。在本文的最后,為方便對本文提出的幾種算法單元進(jìn)行設(shè)計實現(xiàn)、測試及數(shù)據(jù)處理。本文構(gòu)建了一套自動化的處理平臺,并給出了 Design Compiler (DC)綜合后的數(shù)據(jù)。
[Abstract]:And the use of traditional hardware from scale parallelism in different ways, RNS is a parallel numerical characterization system to achieve the method of natural parallel. In recent years, with RSA, ECC as the representative of the public key algorithm widely used RNS framework to improve the encryption speed. With the increase of the length of the secret key, for RNS algorithm unit especially put forward higher requirements and performance under -1 mode 2~n-2~p bit multiplication unit. In addition to conversion as the difficulty of RNS architecture, has been one of the bottlenecks of RNS architecture, {2~n-1,2~n+3,2~n+1,2~n-3} fast backward conversion algorithm is proposed, due to performance problems under 2~n+3 mode multiplication unit and fewer the application system in the application of cryptography. The remainder and fast after conversion to the direction of the latest progress in this paper, according to the special remainder based algorithm unit under the studied by. Research on the classification of a large number of 2~n + 1 multiplier related references, for the design requirements of the architecture were screened. Based on the die is involved in different parts of the binary multiplier multiplier is divided into four types, and in accordance with the execution order of data flow in the name, type 1 were modified, modified type 2, type 3 and type 4 correction correction. According to the classification of this paper, the following work has been done to choose form for the 2~n-2~p-1,2~n+3 remainder based algorithm unit: 1. for the problem of low efficiency of using 2~n -2~p -1 type dynamic range, the use of extension methods available in the literature, the related formula of 2~n-2~p-1 addition to die is reducing its constraints and will be required to determine the correction by A+B + T A + B. for simplification and propose a suitable 2~n-2~p-1 based lossless remainder dynamic algorithm application expansion unit Methods. Using lossless algorithm unit dynamic range expansion mode after the 2~n -2~p -1 adder and multiplier structure in the area is the same X delay efficiency were increased by 41.1% and 12.3%,.2. proposed a type 1 model 2~n-2~p-1 multiplier correction, using properties of 2~n-2~p-1 mode, will contain the negative part of booth encoding selection product might appear in the revised. After the deduction of formula, the modified partial product and correction of separation, the modified partial product can maximize the use of binary booth encoding partial product generation related circuit, finally got a regular part of the product. A universal modular multiplication of this structure when compared with the traditional average the average delay and area were reduced by 49.1% and 6.5%.3. for the correction of type 3 proposed two kinds of mode 2~n-2~p-1 multiplier in booth structure by pre computing To solve the 2~n bit'signed complement representation the partial product is difficult to fix to the N problem. And then obtained a (n, P) unified structure corresponds to the combination of independent. For the first time in the TDM structure and the TDM algorithm is introduced to design the multiplier, deduced a cloth. Encoding is more rapid simplified structure. These two kinds of mode 2~n -2~p -1 multiplier in average delay is highest modulo 2~n- 2~p-1 multiplier current can reduce the 9.7%.4. of 2~n -2~p for the modified type 4 -1,2~n+3 two residue base are proposed for two. In the 2~n -2~p mode multiplier -1 multiplier, the critical path. Use a CSA instead of a p bit binary carry propagation adder, shorten the critical path delay. In 2~n+3 multiplier, using 2~n+3 compression properties in the partial product produced "+9" and "-9" are offset, saving The additional "-9" needed hardware resources. Reduce the critical path delay. Two kinds of structure compared with the same type of current mode multiplier in "area X delay" efficiency were increased by 12.4% and 9.0%. in the end of this article, in the design and implementation of several algorithms for unit convenient for this, and test data processing. This paper constructs a set of automated processing platform, and gives the Design Compiler (DC) after comprehensive data.

【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP332.2

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 魏少軍;;2015年中國集成電路設(shè)計業(yè)的發(fā)展情況[J];集成電路應(yīng)用;2016年01期

相關(guān)博士學(xué)位論文 前1條

1 馬上;基于余數(shù)系統(tǒng)的數(shù)字信號處理VLSI實現(xiàn)關(guān)鍵技術(shù)研究[D];電子科技大學(xué);2009年

相關(guān)碩士學(xué)位論文 前4條

1 嚴(yán)海;余數(shù)系統(tǒng)中模加和模乘單元設(shè)計[D];電子科技大學(xué);2016年

2 李成冬;基于余數(shù)系統(tǒng)的RSA加密運算電路的設(shè)計[D];華南理工大學(xué);2015年

3 趙英旭;余數(shù)系統(tǒng)中余數(shù)基構(gòu)建和數(shù)值縮放的研究[D];電子科技大學(xué);2014年

4 周璐;余數(shù)系統(tǒng)中模加和模乘單元的設(shè)計[D];電子科技大學(xué);2013年

，

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