發(fā)布時(shí)間：2018-03-18 13:40

  本文選題：靜態(tài)存儲(chǔ)單元　切入點(diǎn)：靜態(tài)噪聲容限　出處：《西安電子科技大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著集成電路設(shè)計(jì)水平的提高，對(duì)存儲(chǔ)器高速、低功耗的需求也越來越高。因此，本文在分析virtexII型FPGA的體系結(jié)構(gòu)的基礎(chǔ)上，采用SMIC0.12μm工藝設(shè)計(jì)了一款塊狀存儲(chǔ)器BlockRAM，，重點(diǎn)研究了BRAM主要模塊靜態(tài)存儲(chǔ)單元、靈敏放大器以及外圍電路。 文中設(shè)計(jì)了一種適用于雙端口存儲(chǔ)器的8T SRAM存儲(chǔ)單元結(jié)構(gòu)。這種8TSRAM存儲(chǔ)單元的靜態(tài)噪聲容限可達(dá)到515mV，單元結(jié)構(gòu)抗噪聲能力是同尺寸條件下6T SRAM存儲(chǔ)單元的1.27倍。文中對(duì)傳統(tǒng)差分鎖存型靈敏放大器的結(jié)構(gòu)做了優(yōu)化設(shè)計(jì)，設(shè)計(jì)中引入了預(yù)充電電路和平衡管電路。優(yōu)化后的靈敏放大器數(shù)據(jù)讀取速度僅需176ps，讀取速度是傳統(tǒng)差分鎖存型靈敏放大器的2倍。文中還對(duì)BRAM的主要外圍電路做了設(shè)計(jì)分析，在讀寫控制電路中引入了小脈沖控制電路，小脈沖寬度可以達(dá)到0.842ns。由讀寫控制電路產(chǎn)生的小脈沖信號(hào)作為存儲(chǔ)器的內(nèi)部控制時(shí)鐘可以有效的提高電路穩(wěn)定性。 文中分別采用NC_verilog和nanosim對(duì)所設(shè)計(jì)的BRAM進(jìn)行了仿真，結(jié)果表明文中設(shè)計(jì)的雙端口存儲(chǔ)器可以被配置成數(shù)據(jù)位寬可選的讀寫、只讀或者只寫多種操作模式。大量仿真結(jié)果表明文中設(shè)計(jì)的雙端口存儲(chǔ)器性能良好，能夠在千萬門系統(tǒng)級(jí)FPGA芯片中穩(wěn)定工作。
[Abstract]:With the improvement of IC design level, the demand for high speed and low power consumption of memory is becoming higher and higher. Therefore, based on the analysis of the architecture of virtexII type FPGA, A block memory Block RAM (Block RAM) is designed using SMIC0.12 渭 m technology. The main modules of BRAM, such as static memory cell, sensitive amplifier and peripheral circuit, are studied emphatically. In this paper, an 8TSRAM memory cell structure suitable for dual-port memory is designed. The static noise tolerance of the 8TSRAM memory cell can reach 515mV, and the anti-noise capability of the cell structure is 1.27 times that of the 6T SRAM memory cell with the same size. In this paper, the structure of the traditional differential latch sensitive amplifier is optimized. The precharge circuit and the balance tube circuit are introduced in the design. The data reading speed of the optimized sensitive amplifier is only 176 pss. the reading speed is 2 times that of the traditional differential latch sensitive amplifier. The main peripheral circuits of BRAM are also designed and analyzed. The small pulse control circuit is introduced into the read / write control circuit, and the small pulse width can reach 0.842 ns.The small pulse signal generated by the read / write control circuit as the internal control clock of the memory can effectively improve the stability of the circuit. In this paper, NC_verilog and nanosim are used to simulate the designed BRAM, and the results show that the dual-port memory can be configured to read and write the data bit width. A large number of simulation results show that the dual-port memory designed in this paper has good performance and can work stably in tens of millions of system-level FPGA chips.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333

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本文編號(hào)：1629819