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  本文選題：可靠性　切入點：故障注入　出處：《哈爾濱工業(yè)大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：近年來，計算機技術(shù)呈現(xiàn)出迅猛的發(fā)展態(tài)勢。它所應(yīng)用到的航空、航天等特殊領(lǐng)域要求它要具有很高的可靠性。由于FPGA具有運算快速和編程簡單等優(yōu)點，因此它被廣泛應(yīng)用到航天容錯計算機的設(shè)計當中。近年來，針對這種計算機的可靠性評測也被越來越多的設(shè)計人員所重視。而故障注入技術(shù)是現(xiàn)如今一種重要的可靠性評測方法。故障注入工具的實現(xiàn)則可以為容錯計算機的研究帶來巨大的幫助。 本文針對目前主流故障注入技術(shù)的理論基礎(chǔ)進行了深入的研究，為故障注入工具的實現(xiàn)做好了理論儲備。本文課題來源中的容錯計算機使用了硬件描述語言VHDL。因此，本文主要研究了基于VHDL的故障注入技術(shù)。該技術(shù)中的“突變”方法可以很好的支持注入多種類型的故障，并且不改變目標系統(tǒng)模型的結(jié)構(gòu)�；谶@種技術(shù)，本文設(shè)計并實現(xiàn)了一個故障注入工具。該工具可以對基于VHDL語言建模的系統(tǒng)進行故障注入。它通過分析VHDL源文件中的代碼來找出系統(tǒng)中可以注入的對象，然后使用CASE語句修改源代碼，最后通過仿真器進行故障注入仿真實驗。它可以支持注入多種類型的故障，包括固定0、固定1和位翻轉(zhuǎn)，，同時可以選擇的故障時間為永久故障、瞬時故障和間歇故障。 最后本文使用設(shè)計實現(xiàn)的故障注入工具對課題來源中的容錯計算機進行了多種故障注入實驗，注入對象為該系統(tǒng)容錯機制中的一些重要信號。實驗結(jié)果驗證了系統(tǒng)容錯機制的可靠性。同時，實驗結(jié)果也證明注入工具可以有效地對基于VHDL實現(xiàn)的系統(tǒng)進行故障注入。
[Abstract]:In recent years, computer technology has shown a rapid development trend. The special fields such as aviation and spaceflight require it to have high reliability. Because of the advantages of FPGA, such as fast operation and simple programming, etc. Therefore, it is widely used in the design of aerospace fault-tolerant computer. More and more designers pay attention to the reliability evaluation of this kind of computer. Fault injection technology is an important reliability evaluation method nowadays. The fault injection tool can be implemented as a fault-tolerant computer. The research in 1921 has been of great help. In this paper, the theoretical foundation of the current mainstream fault injection technology is deeply studied, and the theoretical reserve is made for the implementation of the fault injection tool. The fault tolerant computer in the source of this paper uses the hardware description language VHDL. This paper mainly studies the fault injection technology based on VHDL. The "mutation" method in this technology can support the injection of many kinds of faults well, and does not change the structure of the target system model. In this paper, a fault injection tool is designed and implemented. The tool can be used for fault injection of a system based on VHDL language. It finds out the objects that can be injected into the system by analyzing the code in the VHDL source file. Then the source code is modified by using the CASE statement, and the simulation experiment of fault injection is carried out through the simulator. It can support the injection of many kinds of faults, including fixed 0, fixed 1 and bit flip, and the fault time can be chosen as permanent fault. Transient and intermittent failures. Finally, this paper uses the designed and implemented fault injection tools to carry out a variety of fault injection experiments on fault-tolerant computers in the subject source. The injection object is some important signals in the fault-tolerant mechanism of the system. The experimental results verify the reliability of the fault-tolerant mechanism of the system. At the same time, the experimental results also prove that the injection tool can effectively inject the fault of the system based on VHDL.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP302.8

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