基于聯(lián)合仿真的結(jié)構(gòu)級(jí)故障行為研究
發(fā)布時(shí)間:2018-03-11 00:37
本文選題:聯(lián)合仿真 切入點(diǎn):RAS模擬器 出處:《哈爾濱工業(yè)大學(xué)》2013年碩士論文 論文類型:學(xué)位論文
【摘要】:隨著計(jì)算機(jī)爆炸式的發(fā)展,計(jì)算機(jī)系統(tǒng)被廣泛地應(yīng)用于航空、金融、交通、電信、醫(yī)療、教育等與人們生活息息相關(guān)的各行各業(yè)之中,已經(jīng)成為這些行業(yè)當(dāng)中的信息維護(hù)和管理必不可少的基礎(chǔ)設(shè)備。這一特性使得容錯(cuò)計(jì)算的發(fā)展和應(yīng)用更加的廣泛和深入,因此,計(jì)算機(jī)可靠性研究也成為計(jì)算機(jī)的熱門研究領(lǐng)域。然而計(jì)算機(jī)遵循摩爾定律的快速發(fā)展,這就造成集成電路密度增加,從而導(dǎo)致溫度產(chǎn)生的熱效應(yīng)、電流產(chǎn)生的功耗等引發(fā)故障的因素大大增加,使得電路觸發(fā)瞬時(shí)故障、間歇故障或者永久故障的概率也大大增加。為此,開(kāi)展對(duì)處理器硬件故障層次化軟件容錯(cuò)技術(shù)的研究十分有必要。 本課題專注于處理器硬件結(jié)構(gòu)級(jí)的故障行為特性的分析,工作核心是完成一個(gè)基于聯(lián)合仿真的異常事件捕獲系統(tǒng)。從剖析指令RAS(Riesling ArchitectureSimulator)集模擬器和RTL仿真器入手。第一部分工作是分析了系統(tǒng)組成,模擬器流水線和內(nèi)部功能單元等細(xì)節(jié)。再者,設(shè)計(jì)了模擬器與仿真器通訊接口,并定義了異常信號(hào)集,作為異常捕獲系統(tǒng)入口的重要組成部分。 最重要的研究工作是異常捕獲系統(tǒng)的設(shè)計(jì),其是圍繞三大異常捕獲模塊的詳細(xì)設(shè)計(jì)而展開(kāi)的。TLB異常捕獲模塊主要工作是捕獲TLB相關(guān)的異常,并進(jìn)行同步TLB相關(guān)操作;中斷異常捕獲模塊針對(duì)不同的中斷分支捕獲陷阱操作;Memory異常捕獲模塊對(duì)指令預(yù)取和讀寫操作設(shè)計(jì)相應(yīng)的捕獲單元,并維持存儲(chǔ)同步。這樣異常捕獲系統(tǒng)在聯(lián)合仿真進(jìn)行故障注入之際,,能夠自動(dòng)地收集系統(tǒng)交互信息,并捕獲與黃金參考模型不一致的異常癥狀。 最后利用聯(lián)合仿真平臺(tái)進(jìn)行故障注入實(shí)驗(yàn),并啟動(dòng)異常事件捕獲系統(tǒng)。實(shí)驗(yàn)過(guò)程中收集異常癥狀信息,分析大量的實(shí)驗(yàn)數(shù)據(jù),得到故障在結(jié)構(gòu)級(jí)的行為表現(xiàn)和癥狀分布。同時(shí)利用故障癥狀信息作為BP神經(jīng)網(wǎng)絡(luò)的輸入分類特征信息而進(jìn)行故障診斷。
[Abstract]:With the explosive development of computers, computer systems are widely used in aviation, finance, transportation, telecommunications, medical care, education and other industries closely related to people's lives. Has become an essential infrastructure for information maintenance and management in these industries. This feature makes the development and application of fault-tolerant computing more extensive and in-depth, so, Computer reliability research has also become a hot research field of computer. However, the rapid development of computer follows Moore's law, which leads to the increase of integrated circuit density, which leads to the thermal effect of temperature. The power consumption produced by the current has greatly increased the probability of triggering transient fault, intermittent fault or permanent fault, so that the probability of triggering transient fault, intermittent fault or permanent fault is greatly increased. It is necessary to study the fault-tolerant technology of processor hardware. This paper focuses on the analysis of fault behavior at the processor hardware architecture level. The core of the work is to complete an exception event capture system based on joint simulation. The first part of the work is to analyze the composition of the system, starting with the analysis instruction RAS(Riesling Architecture Simulator set simulator and the RTL simulator. Thirdly, the communication interface between simulator and simulator is designed, and the abnormal signal set is defined as an important part of the entrance of the exception capture system. The most important research work is the design of exception capture system, which focuses on the detailed design of three exception capture modules. The main work of the. TLB exception capture module is to catch the exception related to TLB and to synchronize the TLB correlation operation. The interrupt exception capture module designs the corresponding capture unit for different interrupt branch trapping operations: memory exception capture module, instruction prefetching and reading and writing operation. The system can automatically collect the interactive information of the system and catch the abnormal symptoms which are inconsistent with the gold reference model when the fault injection is carried out by the joint simulation. Finally, the fault injection experiment is carried out by using the joint simulation platform, and the abnormal event capture system is started. In the course of the experiment, the abnormal symptom information is collected, and a large number of experimental data are analyzed. At the same time, the fault symptom information is used as the input classification feature information of BP neural network for fault diagnosis.
【學(xué)位授予單位】:哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2013
【分類號(hào)】:TP302.8
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