本文選題：GPS信號(hào)捕獲 + 功能驗(yàn)證��； 參考：《西安電子科技大學(xué)》2013年碩士論文

【摘要】：隨著GPS產(chǎn)品需求的增加，以及集成電路設(shè)計(jì)技術(shù)的快速發(fā)展，越來(lái)越多的公司投身于GPS產(chǎn)品的開(kāi)發(fā)。構(gòu)建一個(gè)通用的GPS信號(hào)處理系統(tǒng)及其驗(yàn)證平臺(tái)，將減少產(chǎn)品設(shè)計(jì)和產(chǎn)品驗(yàn)證的時(shí)間，大大降低產(chǎn)品的研發(fā)周期。本文重點(diǎn)研究了GPS捕獲算法及其硬件實(shí)現(xiàn)技術(shù)，并在此基礎(chǔ)上搭建了分層、可重用、多覆蓋率統(tǒng)計(jì)的驗(yàn)證平臺(tái)。 目前，GPS信號(hào)的捕獲多采用傳統(tǒng)時(shí)域相關(guān)捕獲法，這需要大量硬件資源，實(shí)時(shí)性很差。如果采用FFT并行捕獲方式，將時(shí)域N點(diǎn)相關(guān)運(yùn)算轉(zhuǎn)換到頻域，只需N次乘法運(yùn)算，即可實(shí)現(xiàn)對(duì)一個(gè)載波頻率下的所有C/A碼相位的搜索，相比時(shí)域下的N~2次乘法運(yùn)算，運(yùn)算量大大減小。為滿足FPGA資源要求，本文提出平均采樣技術(shù)，以改進(jìn)FFT并行捕獲法；在不影響捕獲性能的前提下，將中頻數(shù)據(jù)采樣成1024點(diǎn)，最終簡(jiǎn)化硬件實(shí)現(xiàn)過(guò)程。本文在模擬了5000點(diǎn)GPS中頻采樣信號(hào)后，實(shí)現(xiàn)FFT并行捕獲法、改進(jìn)后的FFT并行捕獲法的Matlab仿真，并使用Verilog完成了改進(jìn)方法的FPGA設(shè)計(jì)。結(jié)果顯示，改進(jìn)后的FFT并行捕獲法，可以實(shí)現(xiàn)捕獲功能，且具有較低的硬件資源使用率，硬件實(shí)現(xiàn)方式得以簡(jiǎn)化。 就改進(jìn)后的FPGA設(shè)計(jì)而言，其捕獲部分的驗(yàn)證需要多達(dá)1000個(gè)測(cè)試用例；對(duì)于HDLC幀模塊的驗(yàn)證，至少需要13個(gè)測(cè)試用例。如果手動(dòng)編寫(xiě)，工作量巨大，，且測(cè)試用例不具有重用性，結(jié)果對(duì)比也很費(fèi)精力。本文提出使用System Verilog驗(yàn)證語(yǔ)言，構(gòu)建分層結(jié)構(gòu)的驗(yàn)證平臺(tái)，降低驗(yàn)證組件的關(guān)聯(lián)性，實(shí)現(xiàn)組件重用；應(yīng)用約束化隨機(jī)激勵(lì)、事物級(jí)、覆蓋率統(tǒng)計(jì)、斷言、腳本語(yǔ)言等驗(yàn)證技術(shù)，使用8個(gè)平臺(tái)組件即可實(shí)現(xiàn)大量測(cè)試激勵(lì)生成和輸出信號(hào)自動(dòng)比對(duì)，大大減少測(cè)試用例個(gè)數(shù)，實(shí)現(xiàn)測(cè)試數(shù)據(jù)收集自動(dòng)化，降低工作量。采用代碼覆蓋率、功能覆蓋率、斷言覆蓋率統(tǒng)計(jì)，對(duì)測(cè)試結(jié)果進(jìn)行收集和分析，實(shí)現(xiàn)對(duì)捕獲系統(tǒng)的充分驗(yàn)證。
[Abstract]:With the increase of the demand of GPS products and the rapid development of integrated circuit design technology , more and more companies have invested in the development of GPS products . A universal GPS signal processing system and its verification platform will reduce the time for product design and product verification and greatly reduce the R & D period of the product . This paper focuses on the GPS capture algorithm and its hardware implementation technology , and builds a verification platform of layered , reusable and multi - coverage statistics .

In order to meet the requirements of FPGA resources , the average sampling technique is proposed in this paper to improve the FFT parallel capture method .
In this paper , the IF data is sampled into 1024 points without affecting the capture performance , and finally the hardware realization process is simplified . Based on the simulation of the 5000 - point GPS IF sampling signal , the FFT parallel capture method is realized , the improved FFT parallel acquisition method is simulated , and the FPGA design of the improved method is completed by using verilog . The result shows that the improved FFT parallel acquisition method can realize the capture function , and has lower hardware resource utilization rate , and the hardware implementation mode is simplified .

As far as the improved FPGA design is concerned , the verification of the capture part of the FPGA needs up to 1000 test cases ;
For the verification of HDLC frame module , there are at least 13 test cases . If it is written manually , the workload is huge , and the test cases do not have reusability , the comparison of results is also very energy . This paper presents a verification platform using System verilog to build a hierarchical structure , which can reduce the relevance of the verification component and realize component reuse .
The test results are collected and analyzed with code coverage , function coverage and assertion coverage statistics , and sufficient verification of the acquisition system is realized .
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：P228.4

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 楊鑫;徐偉俊;陳先勇;夏宇聞;;System Verilog中的隨機(jī)化激勵(lì)[J];中國(guó)集成電路;2007年10期

本文編號(hào)：1987516