本文選題：GPS信號捕獲 + 功能驗證��； 參考：《西安電子科技大學(xué)》2013年碩士論文

【摘要】：隨著GPS產(chǎn)品需求的增加，以及集成電路設(shè)計技術(shù)的快速發(fā)展，越來越多的公司投身于GPS產(chǎn)品的開發(fā)。構(gòu)建一個通用的GPS信號處理系統(tǒng)及其驗證平臺，將減少產(chǎn)品設(shè)計和產(chǎn)品驗證的時間，大大降低產(chǎn)品的研發(fā)周期。本文重點研究了GPS捕獲算法及其硬件實現(xiàn)技術(shù)，并在此基礎(chǔ)上搭建了分層、可重用、多覆蓋率統(tǒng)計的驗證平臺。 目前，GPS信號的捕獲多采用傳統(tǒng)時域相關(guān)捕獲法，這需要大量硬件資源，實時性很差。如果采用FFT并行捕獲方式，將時域N點相關(guān)運(yùn)算轉(zhuǎn)換到頻域，只需N次乘法運(yùn)算，即可實現(xiàn)對一個載波頻率下的所有C/A碼相位的搜索，相比時域下的N~2次乘法運(yùn)算，運(yùn)算量大大減小。為滿足FPGA資源要求，本文提出平均采樣技術(shù)，以改進(jìn)FFT并行捕獲法；在不影響捕獲性能的前提下，將中頻數(shù)據(jù)采樣成1024點，最終簡化硬件實現(xiàn)過程。本文在模擬了5000點GPS中頻采樣信號后，實現(xiàn)FFT并行捕獲法、改進(jìn)后的FFT并行捕獲法的Matlab仿真，并使用Verilog完成了改進(jìn)方法的FPGA設(shè)計。結(jié)果顯示，改進(jìn)后的FFT并行捕獲法，可以實現(xiàn)捕獲功能，且具有較低的硬件資源使用率，硬件實現(xiàn)方式得以簡化。 就改進(jìn)后的FPGA設(shè)計而言，其捕獲部分的驗證需要多達(dá)1000個測試用例；對于HDLC幀模塊的驗證，至少需要13個測試用例。如果手動編寫，工作量巨大，，且測試用例不具有重用性，結(jié)果對比也很費(fèi)精力。本文提出使用System Verilog驗證語言，構(gòu)建分層結(jié)構(gòu)的驗證平臺，降低驗證組件的關(guān)聯(lián)性，實現(xiàn)組件重用；應(yīng)用約束化隨機(jī)激勵、事物級、覆蓋率統(tǒng)計、斷言、腳本語言等驗證技術(shù)，使用8個平臺組件即可實現(xiàn)大量測試激勵生成和輸出信號自動比對，大大減少測試用例個數(shù)，實現(xiàn)測試數(shù)據(jù)收集自動化，降低工作量。采用代碼覆蓋率、功能覆蓋率、斷言覆蓋率統(tǒng)計，對測試結(jié)果進(jìn)行收集和分析，實現(xiàn)對捕獲系統(tǒng)的充分驗證。
[Abstract]:With the increase of the demand of GPS products and the rapid development of integrated circuit design technology , more and more companies have invested in the development of GPS products . A universal GPS signal processing system and its verification platform will reduce the time for product design and product verification and greatly reduce the R & D period of the product . This paper focuses on the GPS capture algorithm and its hardware implementation technology , and builds a verification platform of layered , reusable and multi - coverage statistics .

In order to meet the requirements of FPGA resources , the average sampling technique is proposed in this paper to improve the FFT parallel capture method .
In this paper , the IF data is sampled into 1024 points without affecting the capture performance , and finally the hardware realization process is simplified . Based on the simulation of the 5000 - point GPS IF sampling signal , the FFT parallel capture method is realized , the improved FFT parallel acquisition method is simulated , and the FPGA design of the improved method is completed by using verilog . The result shows that the improved FFT parallel acquisition method can realize the capture function , and has lower hardware resource utilization rate , and the hardware implementation mode is simplified .

As far as the improved FPGA design is concerned , the verification of the capture part of the FPGA needs up to 1000 test cases ;
For the verification of HDLC frame module , there are at least 13 test cases . If it is written manually , the workload is huge , and the test cases do not have reusability , the comparison of results is also very energy . This paper presents a verification platform using System verilog to build a hierarchical structure , which can reduce the relevance of the verification component and realize component reuse .
The test results are collected and analyzed with code coverage , function coverage and assertion coverage statistics , and sufficient verification of the acquisition system is realized .
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：P228.4

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 楊鑫;徐偉俊;陳先勇;夏宇聞;;System Verilog中的隨機(jī)化激勵[J];中國集成電路;2007年10期

本文編號：1987516