本文選題：導(dǎo)航抗干擾　切入點(diǎn)：空時(shí)二維處理　出處：《南京理工大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：全球衛(wèi)星導(dǎo)航系統(tǒng)(GPS)衛(wèi)星距離地面較遠(yuǎn),地面接收機(jī)收到的功率較小,極易受壓制式干擾而無法正常工作,本文以某四陣元GPS導(dǎo)航抗壓制式干擾接收機(jī)課題為背景,開展了空時(shí)聯(lián)合自適應(yīng)抗干擾快速實(shí)現(xiàn)算法設(shè)計(jì)與硬件實(shí)現(xiàn)工作。首先,本文針對(duì)四陣元方陣天線,根據(jù)陣列接收信號(hào)模型,完成了 GPS衛(wèi)星信號(hào)和壓制式干擾的建模;針對(duì)GPS衛(wèi)星信號(hào)來向未知場(chǎng)景,本文在傳統(tǒng)功率倒置算法基礎(chǔ)上,設(shè)計(jì)了一種空時(shí)二維抗干擾快速實(shí)現(xiàn)算法,算法運(yùn)算量減小為改進(jìn)前的三分之一;分析了算法的抗干擾性能,評(píng)估了時(shí)延抽頭數(shù)、采樣快拍數(shù)和干擾來向?qū)λ惴ㄐ阅艿挠绊憽Ｆ浯?開展了中頻抗干擾接收機(jī)硬件設(shè)計(jì)與算法軟件實(shí)現(xiàn)工作。完成了基于FPGA+DSP架構(gòu)的中頻抗干擾接收機(jī)原理圖設(shè)計(jì)、PCB設(shè)計(jì)和硬件電路調(diào)試,根據(jù)抗干擾算法架構(gòu),完成了 FPGA和DSP信號(hào)處理任務(wù)分工,其中FPGA主要完成四通道數(shù)字下變頻、協(xié)方差矩陣估算和波束形成處理,DSP主要完成基于功率倒置快速算法的權(quán)重計(jì)算,本文通過對(duì)FPGA軟件設(shè)計(jì)進(jìn)行優(yōu)化,提高了片內(nèi)資源的復(fù)用率,通過對(duì)FPGA程序的時(shí)序優(yōu)化,提高了軟件的穩(wěn)定性,通過對(duì)DSP權(quán)重計(jì)算的匯編優(yōu)化,提高了算法的實(shí)時(shí)性。當(dāng)空時(shí)聯(lián)合抗干擾算法采用四個(gè)陣元與四個(gè)時(shí)延抽頭進(jìn)行權(quán)重計(jì)算時(shí),權(quán)重更新時(shí)間低于0.85ms。最后,本文在室內(nèi)GPS中頻干擾模擬器上完成了中頻抗干擾模塊干擾抑制性能測(cè)試,在外場(chǎng)干擾環(huán)境下完成了四陣元GPS導(dǎo)航抗壓制式干擾接收機(jī)的搜星效果測(cè)試,驗(yàn)證了算法的最大干擾抑制性能。
[Abstract]:Global navigation satellite system (GPS) satellite ground distance is far, the smaller power ground receivers, vulnerable to jamming and can not work normally, based on a four element GPS navigation anti jamming receiver subject as background, the space-time adaptive anti interference algorithm to achieve rapid design and hardware implementation of the work first, according to the four element array antenna, according to the array signal model, completed the GPS satellite signal and suppress jamming for modeling; GPS satellite signal to the unknown scene, based on the traditional power inversion algorithm, designed an anti-jamming space-time fast algorithm, the computational algorithm is reduced in order to improve the anti-jamming performance before 1/3; algorithm analysis, evaluation of the delay tap number, sampling snapshots and interference to affect the performance of the algorithm. Secondly, if carried out anti dry Disturbance receiver hardware design and algorithm software. If completed based on FPGA+DSP anti-jamming receiver principle diagram design, PCB design and debugging of the hardware circuit, according to the anti-jamming algorithm architecture, the completion of the FPGA and DSP signal processing tasks, the main FPGA complete four channel digital down conversion, covariance matrix estimation and beamforming DSP mainly completes the calculation of weight, power inversion based on rapid algorithm, based on FPGA software to optimize the design, improve the reuse rate of on-chip resources, through the timing optimization of the FPGA program, to improve the stability of the software, through the assembly optimization calculation of the weight of DSP, improved the real-time performance of the algorithm in the sky. Anti jamming algorithm using four antennas and four delay tap weight calculation, the weight update time is less than 0.85ms., the indoor GPS interference The interference suppression performance test of the intermediate frequency anti-jamming module has been completed on the simulator. Under the external field interference environment, we have completed the search effect test of the four element GPS navigation anti jamming jamming receiver, and verified the maximum interference suppression performance of the algorithm.

【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：P228.4

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