FPGA可重構(gòu)計算的規(guī)模可伸縮性研究及實現(xiàn)
發(fā)布時間：2019-04-19 04:36
【摘要】：隨著信息技術(shù)的快速發(fā)展,大數(shù)據(jù)、物聯(lián)網(wǎng)、人工智能等熱點產(chǎn)業(yè)所帶來的信息量逐漸增大,這些產(chǎn)業(yè)對數(shù)據(jù)的高性能處理越來越迫切。然而,受到半導(dǎo)體工藝的限制,處理器的性能已難以滿足應(yīng)對高性能計算的需求。取而代之的是多核、眾核等同構(gòu)多核處理器,但是一旦同構(gòu)多核處理器的計算性能達到一定極限后,則無法再隨著內(nèi)核數(shù)量的增加而提升。研究發(fā)現(xiàn),CPU與FPGA的異構(gòu)多核處理器能夠滿足大數(shù)據(jù)處理的計算效率,且功耗相對較低。然而盡管CPU-FPGA異構(gòu)系統(tǒng)在高性能計算領(lǐng)域具有良好的優(yōu)勢,但其并沒有得到大規(guī)模應(yīng)用。主要原因有,相比于通用計算機系統(tǒng),FPGA的開發(fā)效率低,并且FPGA的計算模式的規(guī)�？缮炜s性差。用戶在使用FPGA開發(fā)時,受到器件物理資源的限制,如果FPGA開發(fā)者不提供源代碼,已開發(fā)好的應(yīng)用很難部署到不同的FPGA器件上,限制了成果的大規(guī)模傳播和應(yīng)用。本文基于動態(tài)部分可重構(gòu)技術(shù)及虛擬存儲池機制,實現(xiàn)了FPGA可重構(gòu)計算的規(guī)�？缮炜s性機制,主要實現(xiàn)包括:將FPGA資源劃分成物理資源與邏輯資源,使得用戶在進行FPGA應(yīng)用開發(fā)時,不再受物理資源的限制,僅需滿足邏輯資源大小。為保證適應(yīng)多種不同類型的應(yīng)用加速,采取分等級的固定頁面劃分機制,頁面間具有一定的兼容性,可組合調(diào)入。頁面間實現(xiàn)了共享內(nèi)存式和流水式兩種通信方式。此外,為了推動FPGA大規(guī)模應(yīng)用,改善其開發(fā)效率,本文提供了一套基于設(shè)計重用及解耦合思想的開發(fā)模式,鼓舞開發(fā)者分享FPGA應(yīng)用成果,同時方便了用戶進行應(yīng)用開發(fā),體驗FPGA應(yīng)用的性能加速。本文實現(xiàn)的FPGA可重構(gòu)計算的規(guī)�？缮炜s性架構(gòu)在FPGA中支持SIMD/MIMD并行計算模式,并通過可重構(gòu)計算單元的通信支持流水式計算模式,方便用戶根據(jù)具體應(yīng)用選擇相應(yīng)的計算模式,從而達到最大的計算效率。實驗結(jié)果顯示,相比較其它平臺及傳統(tǒng)FPGA應(yīng)用,該架構(gòu)在保持FPGA計算系統(tǒng)高性能、低功耗優(yōu)勢的同時,能有效地簡化用戶的編程模式,有利于推動FPGA成果的大規(guī)模傳播和應(yīng)用。
[Abstract]:With the rapid development of information technology, the amount of information brought by hot industries such as big data, Internet of things, artificial intelligence and so on increases gradually, and the high-performance processing of data in these industries is becoming more and more urgent. However, due to the limitations of semiconductor technology, the performance of the processor is difficult to meet the needs of high-performance computing. Instead of multi-core and multi-core isomorphic multi-core processors, once the computing performance of isomorphic multi-core processors reaches a certain limit, it can no longer be improved with the increase of the number of cores. It is found that the heterogeneous multicore processors of CPU and FPGA can satisfy the computing efficiency of big data and the power consumption is relatively low. However, although CPU-FPGA heterogeneous systems have good advantages in the field of high performance computing, they have not been applied on a large scale. The main reasons are that compared with the general computer system, the development efficiency of FPGA is low, and the scale scalability of FPGA computing mode is poor. When users use FPGA, they are limited by the physical resources of devices. If FPGA developers do not provide source code, it is difficult to deploy well-developed applications to different FPGA devices, which limits the large-scale dissemination and application of the results. Based on dynamic partial reconfigurable technology and virtual storage pool mechanism, the scale scalability mechanism of FPGA reconfigurable computing is realized in this paper. The main realization includes: dividing FPGA resources into physical resources and logical resources. When users are developing FPGA applications, they are no longer limited by physical resources, and only need to satisfy the logical resource size. In order to adapt to a variety of different types of application acceleration, a hierarchical fixed page partition mechanism is adopted, which has certain compatibility among pages and can be combined into. Pages between the realization of shared memory and flow of two types of communication mode. In addition, in order to promote the large-scale application of FPGA and improve its development efficiency, this paper provides a set of development mode based on the idea of design reuse and decoupling, which encourages developers to share the results of FPGA application, and at the same time makes it convenient for users to carry out application development. Experience performance acceleration for FPGA applications. The scale scalability architecture of FPGA reconfigurable computing implemented in this paper supports the SIMD/MIMD parallel computing pattern in FPGA, and supports the flowing water computing pattern through the communication of reconfigurable computing units. It is convenient for the user to choose the corresponding calculation mode according to the specific application, so as to achieve the maximum calculation efficiency. The experimental results show that compared with other platforms and traditional FPGA applications, this architecture not only keeps the high performance and low power consumption advantage of FPGA computing system, but also simplifies the programming mode of users effectively, and is helpful to promote the large-scale dissemination and application of FPGA achievements.
【學(xué)位授予單位】：江南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN791
本文編號：2460606
[Abstract]:With the rapid development of information technology, the amount of information brought by hot industries such as big data, Internet of things, artificial intelligence and so on increases gradually, and the high-performance processing of data in these industries is becoming more and more urgent. However, due to the limitations of semiconductor technology, the performance of the processor is difficult to meet the needs of high-performance computing. Instead of multi-core and multi-core isomorphic multi-core processors, once the computing performance of isomorphic multi-core processors reaches a certain limit, it can no longer be improved with the increase of the number of cores. It is found that the heterogeneous multicore processors of CPU and FPGA can satisfy the computing efficiency of big data and the power consumption is relatively low. However, although CPU-FPGA heterogeneous systems have good advantages in the field of high performance computing, they have not been applied on a large scale. The main reasons are that compared with the general computer system, the development efficiency of FPGA is low, and the scale scalability of FPGA computing mode is poor. When users use FPGA, they are limited by the physical resources of devices. If FPGA developers do not provide source code, it is difficult to deploy well-developed applications to different FPGA devices, which limits the large-scale dissemination and application of the results. Based on dynamic partial reconfigurable technology and virtual storage pool mechanism, the scale scalability mechanism of FPGA reconfigurable computing is realized in this paper. The main realization includes: dividing FPGA resources into physical resources and logical resources. When users are developing FPGA applications, they are no longer limited by physical resources, and only need to satisfy the logical resource size. In order to adapt to a variety of different types of application acceleration, a hierarchical fixed page partition mechanism is adopted, which has certain compatibility among pages and can be combined into. Pages between the realization of shared memory and flow of two types of communication mode. In addition, in order to promote the large-scale application of FPGA and improve its development efficiency, this paper provides a set of development mode based on the idea of design reuse and decoupling, which encourages developers to share the results of FPGA application, and at the same time makes it convenient for users to carry out application development. Experience performance acceleration for FPGA applications. The scale scalability architecture of FPGA reconfigurable computing implemented in this paper supports the SIMD/MIMD parallel computing pattern in FPGA, and supports the flowing water computing pattern through the communication of reconfigurable computing units. It is convenient for the user to choose the corresponding calculation mode according to the specific application, so as to achieve the maximum calculation efficiency. The experimental results show that compared with other platforms and traditional FPGA applications, this architecture not only keeps the high performance and low power consumption advantage of FPGA computing system, but also simplifies the programming mode of users effectively, and is helpful to promote the large-scale dissemination and application of FPGA achievements.
【學(xué)位授予單位】：江南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN791
【參考文獻】
相關(guān)期刊論文 前6條
1 馬飛;劉琦;尹娜;包斌;;Tcl/Tk語言FPGA邏輯IP庫實現(xiàn)方法研究[J];電子測量技術(shù);2014年01期
2 毛熠;陳娜;;MD5算法的研究與改進[J];計算機工程;2012年24期
3 孫俊杰;;面向未來十年賽靈思打造Vivado[J];中國電子商情(基礎(chǔ)電子);2012年05期
4 Mike Santarini;;Zynq-7000 EPP為創(chuàng)新開啟新時代[J];電子技術(shù)應(yīng)用;2011年07期
5 黃國睿;張平;魏廣博;;多核處理器的關(guān)鍵技術(shù)及其發(fā)展趨勢[J];計算機工程與設(shè)計;2009年10期
6 胡峰,胡保生;并行計算技術(shù)與并行算法綜述[J];電腦與信息技術(shù);1999年05期
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