采用SMIC 0.13μm定制化工藝標準單元庫的TOF芯片專用TDC模塊設計
發(fā)布時間：2019-04-18 07:45
【摘要】：TOF(Time-of-Flight,飛行時間)芯片是一種精確測量場景深度信息的傳感器,廣泛應用于軍事、航天航空、導航通信等國防建設的激光測距領域。由于TOF芯片使用單光子發(fā)射到遇物體而反射回來的時間來記錄衡量深度信息,因此單光子的飛行時間量化是TOF芯片的關鍵技術。時間相關單光子計數(shù)技術(Time-correlated single-photon counting,TCSPC)應用于TOF芯片中,能夠將飛行時間通過時鐘計數(shù)的方式量化讀出,其精度的高低決定了芯片性能的好壞。時間數(shù)字轉換(Time-to-Digital Converter,TDC)電路是TCSPC技術的核心模塊。為了實現(xiàn)高精度的TDC電路,本文設計的TDC電路包括三個模塊,分別為TDC控制模塊,TDC測量模塊和TDC譯碼模塊。TDC控制模塊用于控制TDC測量模塊的工作狀態(tài)。TDC測量模塊采用三級結構:第一級TDC是采用時間周期計數(shù)法的粗精度測量,后兩級TDC是采用游標型的細精度測量。TDC譯碼模塊利用本文創(chuàng)建的基于SMIC 0.13μm工藝的標準單元庫進行半定制集成電路設計與版圖實現(xiàn)。本文采用的半定制集成電路設計流程為:首先進行Verilog代碼定制譯碼模塊電路的程序,使用Modelsim工具進行譯碼模塊功能仿真;然后定義基于SMIC 0.13μm工藝標準單元的規(guī)格和性能等參數(shù),設計單元的版圖并進行驗證,通過驗證后將標準單元制作成用于數(shù)字后端工具的標準單元庫;最后通過Synopsys工具的Design Compiler和IC Compiler進行綜合和自動布局布線完成TDC模塊電路的版圖設計,并制成GDSII文件并在Cadence工具下進行設計規(guī)則以及后仿真的驗證。本文的設計成果包括:1)搭建TDC控制與測量模塊電路,設計三級測量結構提高TDC電路的分辨率和精度。2)設計8種基本邏輯單元,構成一個實用的SMIC 0.13μm標準單元庫,并為每個標準單元設置了不同驅動能力用于綜合和自動布局布線時的時序優(yōu)化。3)在創(chuàng)建的標準單元庫在Synopsys的綜合工具和布局布線工具上進行TDC模塊版圖的自動生成,同時利用Cadence Virtuoso工具驗證版圖的功能。
[Abstract]:TOF (time-of-flight) chip is a kind of sensor for accurate measurement of depth information of scene. It is widely used in the field of laser ranging in military, aerospace, navigation, communication and other national defense construction. Since the TOF chip records the depth information using the time of reflection from the single photon emission to the object, the quantization of the flight time of the single photon is the key technology of the TOF chip. Time-dependent single photon counting (Time-correlated single-photon counting,TCSPC) is used in TOF chip, and the flight time can be read out quantitatively by clock counting. Its precision determines the performance of the chip. Time-to-digital conversion (Time-to-Digital Converter,TDC) circuit is the core module of TCSPC technology. In order to realize the high precision TDC circuit, the TDC circuit designed in this paper includes three modules, which are the TDC control module, respectively. TDC measurement module and TDC decoding module. TDC control module is used to control the working status of TDC measurement module. TDC measurement module adopts three-level structure: the first stage TDC is coarse precision measurement using time period counting method. The latter two stages of TDC are fine precision measurement using cursors. TDC decoding module uses the standard cell library based on SMIC 0.13 渭 m process established in this paper to design the semi-custom integrated circuit and realize the layout. The design flow of semi-custom integrated circuit in this paper is as follows: firstly, the program of Verilog code custom decoding module circuit is carried out, and the function simulation of decoding module is carried out by using Modelsim tool; Then the specification and performance of SMIC 0.13 渭 m process standard unit are defined, and the layout of the unit is designed and verified. After the verification, the standard unit is made into a standard cell library for digital back-end tools. Finally, the layout design of TDC module circuit is completed by Design Compiler and IC Compiler of Synopsys tool, and the layout design of TDC module circuit is completed. The GDSII file is made, and the design rules and post-simulation are verified under the Cadence tool. The design results of this paper include: 1) build TDC control and measurement module circuit, design three-level measurement structure to improve the resolution and precision of TDC circuit. 2) Design 8 kinds of basic logic units to form a practical standard cell library of SMIC 0.13 渭 m. Different driving ability is set for each standard cell to optimize the timing of synthesis and automatic routing. 3) automatic generation of TDC module layout on Synopsys synthesis tool and layout tool is carried out in the created standard cell library. At the same time, the Cadence Virtuoso tool is used to verify the function of the layout.
【學位授予單位】：深圳大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN402
本文編號：2459872
[Abstract]:TOF (time-of-flight) chip is a kind of sensor for accurate measurement of depth information of scene. It is widely used in the field of laser ranging in military, aerospace, navigation, communication and other national defense construction. Since the TOF chip records the depth information using the time of reflection from the single photon emission to the object, the quantization of the flight time of the single photon is the key technology of the TOF chip. Time-dependent single photon counting (Time-correlated single-photon counting,TCSPC) is used in TOF chip, and the flight time can be read out quantitatively by clock counting. Its precision determines the performance of the chip. Time-to-digital conversion (Time-to-Digital Converter,TDC) circuit is the core module of TCSPC technology. In order to realize the high precision TDC circuit, the TDC circuit designed in this paper includes three modules, which are the TDC control module, respectively. TDC measurement module and TDC decoding module. TDC control module is used to control the working status of TDC measurement module. TDC measurement module adopts three-level structure: the first stage TDC is coarse precision measurement using time period counting method. The latter two stages of TDC are fine precision measurement using cursors. TDC decoding module uses the standard cell library based on SMIC 0.13 渭 m process established in this paper to design the semi-custom integrated circuit and realize the layout. The design flow of semi-custom integrated circuit in this paper is as follows: firstly, the program of Verilog code custom decoding module circuit is carried out, and the function simulation of decoding module is carried out by using Modelsim tool; Then the specification and performance of SMIC 0.13 渭 m process standard unit are defined, and the layout of the unit is designed and verified. After the verification, the standard unit is made into a standard cell library for digital back-end tools. Finally, the layout design of TDC module circuit is completed by Design Compiler and IC Compiler of Synopsys tool, and the layout design of TDC module circuit is completed. The GDSII file is made, and the design rules and post-simulation are verified under the Cadence tool. The design results of this paper include: 1) build TDC control and measurement module circuit, design three-level measurement structure to improve the resolution and precision of TDC circuit. 2) Design 8 kinds of basic logic units to form a practical standard cell library of SMIC 0.13 渭 m. Different driving ability is set for each standard cell to optimize the timing of synthesis and automatic routing. 3) automatic generation of TDC module layout on Synopsys synthesis tool and layout tool is carried out in the created standard cell library. At the same time, the Cadence Virtuoso tool is used to verify the function of the layout.
【學位授予單位】：深圳大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN402
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