TFET單元庫設計技術(shù)研究
發(fā)布時間：2019-03-13 15:46
【摘要】：TFET作為新型的低功耗器件,物理結(jié)構(gòu)上采用源漏區(qū)非對稱性摻雜,通過外加柵電壓控制能帶偏移,進而利用隧道擊穿原理實現(xiàn)器件工作。與傳統(tǒng)漂移擴散機制MOSFET器件相比,TFET器件的亞閾值斜率能夠突破60m V/dec的限制,能夠在較低電源電壓下獲得更大的電流開關(guān)比,從而實現(xiàn)超低功耗的目標。數(shù)字標準單元庫是集成電路設計自動化的關(guān)鍵,是銜接前端設計與后端物理實現(xiàn)的橋梁。本文在基于傳統(tǒng)MOSFET建庫技術(shù)基礎(chǔ)上,探究了TFET應用的研究方向,將TFET器件應用于數(shù)字標準單元庫設計上。在已有技術(shù)的基礎(chǔ)上,利用TFET器件模型,進行了相關(guān)研究,并在單元設計、版圖規(guī)劃和器件檢測方面取得一定成果�；趥鹘y(tǒng)工藝的MOSFET器件,進行了建庫工作,包含庫單元的原理圖提取及優(yōu)化,特性仿真和版圖繪制,并利用已有的庫單元,完成整體的建庫流程,包含最重要的各類庫文件生成及相應腳本文件編寫。在單元設計中,針對單元的組合邏輯和時序邏輯電路進行深入研究,并結(jié)合TFET器件模型,對傳輸門邏輯對整體電路的設計影響進行分析,進而對比選擇適合TFET器件的電路設計結(jié)構(gòu);另外,根據(jù)現(xiàn)有的模型兼容性問題,設計了測試觸發(fā)器電路建立時間和保持時間的雙時鐘邊沿測試電路。在版圖規(guī)劃方面,依據(jù)流片測試的版圖模型并結(jié)合單元庫設計方案,對單元版圖進行了規(guī)劃,并針對TFET器件的版圖檢測進行研究,修改了相應DRC檢測規(guī)則使之能夠針對TFET器件的特殊結(jié)構(gòu)進行檢測,其中包含針對一般類型的TFET器件,以及包含Pocket結(jié)構(gòu)和Underlap結(jié)構(gòu)的特殊類型TFET器件。
[Abstract]:As a new type of low-power device, TFET adopts asymmetric doping in the source-drain region in physical structure, and controls the energy band offset by the external gate voltage, and then realizes the device work by using the tunneling breakdown principle. Compared with the traditional drift-diffusion mechanism MOSFET devices, the sub-threshold slope of TFET devices can break through the limit of 60m V/dec and achieve higher current-switching ratio at lower power supply voltage, thus achieving the goal of ultra-low power consumption. Digital standard cell library is the key of IC design automation and the bridge between front-end design and back-end physical implementation. Based on the traditional MOSFET technology, this paper explores the research direction of TFET application, and applies the TFET device to the design of digital standard cell library. On the basis of the existing technology, the TFET device model is used to do some research, and some achievements in cell design, layout planning and device detection are obtained. Based on the traditional technology of MOSFET device, the library is built, which includes the extraction and optimization of the schematic diagram of the library unit, the simulation of the characteristics and the drawing of the layout, and using the existing library unit to complete the whole process of building the library. Contains the most important types of library file generation and the corresponding script file writing. In the unit design, the combinatorial logic and the sequential logic circuit of the unit are deeply studied, and the influence of the transmission gate logic on the design of the whole circuit is analyzed based on the TFET device model. Then the circuit design structure suitable for TFET devices is compared and selected. In addition, according to the compatibility problem of the existing model, a double clock edge test circuit is designed for setting up time and holding time of the trigger circuit. In the aspect of layout planning, according to the layout model of flow sheet test and the design scheme of cell library, the layout planning of unit layout is carried out, and the layout detection of TFET devices is studied. The corresponding DRC detection rules are modified to detect the special structure of TFET devices including TFET devices for general types and special types of TFET devices including Pocket structures and Underlap structures.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386
本文編號：2439531
[Abstract]:As a new type of low-power device, TFET adopts asymmetric doping in the source-drain region in physical structure, and controls the energy band offset by the external gate voltage, and then realizes the device work by using the tunneling breakdown principle. Compared with the traditional drift-diffusion mechanism MOSFET devices, the sub-threshold slope of TFET devices can break through the limit of 60m V/dec and achieve higher current-switching ratio at lower power supply voltage, thus achieving the goal of ultra-low power consumption. Digital standard cell library is the key of IC design automation and the bridge between front-end design and back-end physical implementation. Based on the traditional MOSFET technology, this paper explores the research direction of TFET application, and applies the TFET device to the design of digital standard cell library. On the basis of the existing technology, the TFET device model is used to do some research, and some achievements in cell design, layout planning and device detection are obtained. Based on the traditional technology of MOSFET device, the library is built, which includes the extraction and optimization of the schematic diagram of the library unit, the simulation of the characteristics and the drawing of the layout, and using the existing library unit to complete the whole process of building the library. Contains the most important types of library file generation and the corresponding script file writing. In the unit design, the combinatorial logic and the sequential logic circuit of the unit are deeply studied, and the influence of the transmission gate logic on the design of the whole circuit is analyzed based on the TFET device model. Then the circuit design structure suitable for TFET devices is compared and selected. In addition, according to the compatibility problem of the existing model, a double clock edge test circuit is designed for setting up time and holding time of the trigger circuit. In the aspect of layout planning, according to the layout model of flow sheet test and the design scheme of cell library, the layout planning of unit layout is carried out, and the layout detection of TFET devices is studied. The corresponding DRC detection rules are modified to detect the special structure of TFET devices including TFET devices for general types and special types of TFET devices including Pocket structures and Underlap structures.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386
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