【摘要】：集成電路工藝水平的發(fā)展使得特征尺寸減小、臨界電荷量變低,電路很容易受到外界影響而產(chǎn)生故障。不論是宇宙太空中,還是我們賴以生存的大氣層中,都存在著影響集成電路可靠性的輻射粒子。高能輻射粒子撞擊器件的靈敏區(qū),會(huì)使其發(fā)生電離效應(yīng),產(chǎn)生高密度的電子空穴對(duì),影響電路穩(wěn)定性。輻射造成的錯(cuò)誤分為軟錯(cuò)誤和硬錯(cuò)誤,硬錯(cuò)誤是永久性損傷,而軟錯(cuò)誤是瞬時(shí)錯(cuò)誤,對(duì)器件本身沒(méi)有損傷,可以恢復(fù)。本文主要研究晶體管級(jí)和邏輯級(jí)的數(shù)字集成電路軟錯(cuò)誤防護(hù)方法。首先,針對(duì)幾種國(guó)內(nèi)外已有的晶體管和邏輯級(jí)容錯(cuò)技術(shù)進(jìn)行探究,對(duì)各種容錯(cuò)電路結(jié)構(gòu)進(jìn)行原理分析和電路仿真,并驗(yàn)證其軟錯(cuò)誤防護(hù)性能。接著,本文提出了一種晶體管級(jí)的軟錯(cuò)誤防護(hù)方案——開關(guān)型冗余加固脈沖觸發(fā)器,同樣對(duì)它進(jìn)行電路仿真與容錯(cuò)驗(yàn)證。由仿真結(jié)果可知,此觸發(fā)器具有良好的容錯(cuò)性能,能夠防護(hù)大部分關(guān)鍵節(jié)點(diǎn)發(fā)生的軟錯(cuò)誤。最后,本文采用層次化的全定制設(shè)計(jì)方法,對(duì)開關(guān)型冗余加固脈沖觸發(fā)器進(jìn)行投片與測(cè)試,以驗(yàn)證它的基本功能與軟錯(cuò)誤防護(hù)性能。本文的創(chuàng)新點(diǎn)在于提出了開關(guān)型冗余加固脈沖觸發(fā)器結(jié)構(gòu)。此觸發(fā)器以一定的面積代價(jià)換取軟錯(cuò)誤防護(hù)性能的提高。本文首先提出了開關(guān)型脈沖觸發(fā)器結(jié)構(gòu),此脈沖觸發(fā)器的晶體管數(shù)目較少,并且由于是脈沖觸發(fā)器,因此它的時(shí)鐘負(fù)載較小。在開關(guān)型脈沖觸發(fā)器的基礎(chǔ)上,增加部分冗余電路,并結(jié)合C單元,設(shè)計(jì)出具有軟錯(cuò)誤防護(hù)功能的脈沖觸發(fā)器。冗余電路的增加使得開關(guān)型冗余加固脈沖觸發(fā)器晶體管數(shù)目增多,相比于標(biāo)準(zhǔn)單元,付出了一定的面積代價(jià)。本文的不足之處在于只對(duì)樣片進(jìn)行了基本功能測(cè)試,由于條件原因,輻照實(shí)驗(yàn)未能完成。但是從原理分析以及電路仿真結(jié)果來(lái)看,此觸發(fā)器具有較好的軟錯(cuò)誤防護(hù)性能,能夠防護(hù)大部分關(guān)鍵節(jié)點(diǎn)的軟錯(cuò)誤。開關(guān)型冗余加固脈沖觸發(fā)器以部分面積代價(jià)換取良好的容錯(cuò)性能。相比于標(biāo)準(zhǔn)單元,它的面積增加了69%,功耗也會(huì)相應(yīng)的增加。但是對(duì)于可靠性要求較高的集成電路來(lái)說(shuō),以部分面積和功耗代價(jià)來(lái)?yè)Q取性能的穩(wěn)定是很值得的。而且,與傳統(tǒng)的軟錯(cuò)誤防護(hù)技術(shù)相比,該觸發(fā)器所付出的面積代價(jià)較小,并且不需要浪費(fèi)額外的時(shí)鐘周期,可行性較強(qiáng)。
[Abstract]:With the development of integrated circuit technology, the characteristic size is reduced, the critical charge is reduced, and the circuit is easily affected by the outside world. Whether in space or in the atmosphere on which we live, there are radioactive particles that affect the reliability of integrated circuits. The high energy radiation particles impact the sensitive region of the device, which will cause ionization effect and produce high density electron hole pairs, which will affect the stability of the circuit. The errors caused by radiation can be divided into soft error and hard error, hard error is permanent damage, and soft error is instantaneous error, which has no damage to the device itself and can be recovered. In this paper, the methods of digital integrated circuit soft error protection at transistor level and logic level are studied. Firstly, several kinds of transistor and logic level fault-tolerant technology are studied, the principle analysis and circuit simulation of various fault-tolerant circuit structures are carried out, and the performance of soft error prevention is verified. Then, this paper presents a kind of soft error protection scheme at transistor level, which is the switch type redundant strengthened pulse trigger, which is also simulated and fault-tolerant. The simulation results show that the flip-flop has good fault-tolerant performance and can protect most key nodes from soft errors. Finally, in order to verify its basic function and soft error prevention performance, this paper adopts a hierarchical, fully customized design method to cast and test the switch redundancy reinforced pulse flip-flop. The innovation of this paper lies in the structure of switched redundancy reinforced pulse flip-flop. This flip-flop trades for the improvement of the performance of soft error protection at a certain area cost. In this paper, a switch type pulse flip-flop structure is proposed. The number of transistors in this pulse flip-flop is small, and its clock load is small because it is a pulse flip-flop. On the basis of switching pulse flip-flop, a pulse flip-flop with soft error protection is designed by adding some redundant circuits and combining with C unit. With the increase of redundant circuits, the number of switched redundancy strengthened pulse trigger transistors increases, which pays a certain area cost compared with the standard cells. The shortcoming of this paper is that the basic function of the sample has been tested only, but the irradiation experiment has not been completed because of the condition. But from the analysis of principle and the result of circuit simulation, it is shown that this trigger has better performance of soft error prevention and can protect most key nodes from soft error. Switching redundancy strengthened pulse flip-flop gains good fault-tolerant performance at partial area cost. Compared with the standard cell, its area increases 69 and the power consumption increases accordingly. However, for integrated circuits with high reliability requirements, it is worth paying for performance stability at the cost of partial area and power consumption. In addition, compared with the traditional soft error prevention technology, this trigger has less area cost, and does not need to waste additional clock cycles, so it is more feasible.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN783

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本文編號(hào)：2337051