【摘要】：性能和功耗是評價一款芯片優(yōu)良的重要指標。隨著芯片的集成度越來越高,工藝的特征尺寸越來越小,使得芯片設計的復雜程度成倍增長,導致芯片物理設計的工作壓力越來越大。同時,電壓降、串擾、繞線、擁塞等因素對于芯片性能和功耗的影響越來越大,這些因素對芯片性能和功耗優(yōu)化工作提出了新的挑戰(zhàn)。本文對FT-DX芯片ALU部件的固化設計做了細致的研究,為了縮短設計周期,并且取得較好的時序結果,對ALU部件的物理設計采用了半定制設計方法,使用腳本結合EDA工具完成初步優(yōu)化,對其中的關鍵路徑和局部時鐘樹重構做了手工的優(yōu)化。通過本文方法的優(yōu)化,ALU部件的時序結果與單純使用EDA工具進行優(yōu)化的結果相比,時序優(yōu)化了31%,消除了97%的建立時間檢查違反路徑,迭代周期縮減了約50%。本文對掃描鏈在物理設計中的影響進行了深入分析。為了減小掃描鏈路占用的布局資源,減小測試模式下掃描鏈路的時序違反和功耗,本文提出了一種結合掃描單元物理位置信息的掃描鏈定序方法。此方法通過減少掃描鏈路中插入的緩沖器數(shù)目和減少繞線,合理排列掃描單元連接順序,來達到降低掃描鏈路占用的布線資源,減少測試模式下掃描鏈路保持時間檢查違反和降低測試模式下掃描鏈路功耗的目的,并對傳統(tǒng)的物理設計流程進行了改進。結合FT-DX芯片的ALU部件,對本文方法進行了實踐檢驗,結果證明,本文的掃描鏈定序方法與傳統(tǒng)方法相比,測試功耗降低了1.12%,總時序優(yōu)化了4.1%。本文提出了一種通過縮減非關鍵路徑上單元尺寸來降低功耗、減小保持時間檢查違反和布局資源的方法。通過結合Power Explorer工具,縮減非關鍵路徑上有優(yōu)化余量的單元的尺寸的方法,對傳統(tǒng)的物理設計優(yōu)化流程進行了改進。結合FT-DX芯片的ALU部件對本文提出的尺寸縮減方法進行了實踐檢驗,結果證明本文提出的方法確實可以有效降低非關鍵路徑的功耗,比單純使用Power Explorer工具進行功耗優(yōu)化所取得的好處增加了一倍。
[Abstract]:Performance and power consumption are important indexes to evaluate a chip. With the increasing integration of the chip, the characteristic size of the process becomes smaller and smaller, which makes the complexity of the chip design increase exponentially, resulting in the working pressure of the chip physical design is increasing. At the same time, voltage drop, crosstalk, wire winding, congestion and other factors have more and more influence on chip performance and power consumption. These factors pose a new challenge to chip performance and power optimization. In this paper, the solidification design of ALU parts of FT-DX chip is studied in detail. In order to shorten the design period and obtain better timing results, the semi-custom design method is used for the physical design of ALU parts. The script combined with EDA tool is used to optimize the critical path and local clock tree by hand. Through the optimization of the method in this paper, the timing results of ALU parts are optimized by 31%, 97% of the setup time is eliminated, and the iteration period is reduced by about 50% compared with the results of simple optimization using EDA tools. In this paper, the influence of scanning chain on physical design is analyzed. In order to reduce the layout resource occupied by the scanning link and to reduce the timing violation and power consumption of the scan link in test mode, a scanning chain ordering method combining the physical location information of the scanning unit is proposed in this paper. By reducing the number of buffers inserted in the scanning link, reducing the winding and arranging the connection order of the scanning unit reasonably, the method can reduce the wiring resources occupied by the scanning link. The purpose of reducing scan link holding time in test mode to check violation and to reduce the power consumption of scan link in test mode is discussed, and the traditional physical design flow is improved. Combined with the ALU part of FT-DX chip, the method is tested. The results show that compared with the traditional method, the test power consumption is reduced by 1.12 and the total timing is optimized by 4.1. In this paper, we propose a method to reduce power consumption and hold time to check violations and layout resources by reducing cell size on non-critical paths. The traditional physical design optimization process is improved by using the Power Explorer tool to reduce the size of the unit with an optimization margin on the non-critical path. The size reduction method proposed in this paper is tested with the ALU part of FT-DX chip. The results show that the proposed method can effectively reduce the power consumption of non-critical path. The benefits of power optimization are more than double that of using Power Explorer tools alone.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402

【相似文獻】

相關期刊論文 前10條

1 王冠軍;趙瑩;王茂勵;;考慮測試功耗的掃描鏈劃分新方法[J];微電子學與計算機;2010年01期

2 鄧立寶;俞洋;江麗君;;基于自動分段離均差的掃描鏈平衡算法[J];儀器儀表學報;2013年06期

3 李兆麟,葉以正,毛志剛;通過單掃描鏈的構造實現(xiàn)最小測試應用時間[J];計算機學報;1999年12期

4 李兆麟,葉以正;全掃描設計中多掃描鏈的構造[J];電子學報;2000年02期

5 陳治國,徐勇軍,李曉維;一種基于概率分析的掃描鏈動態(tài)功耗模型[J];微電子學與計算機;2004年02期

6 歐陽一鳴;劉娟;梁華國;陳田;;一種基于選擇觸發(fā)的低功耗掃描鏈結構[J];計算機工程與應用;2010年01期

7 王澤成;尤志強;;基于掃描鏈阻塞技術的時延測試方法[J];計算機工程;2012年04期

8 劉杰;梁華國;易茂祥;趙發(fā)勇;;動態(tài)向量調(diào)整的多掃描鏈測試數(shù)據(jù)壓縮[J];電子學報;2012年02期

9 于靜;梁華國;蔣翠云;;基于多掃描鏈相容壓縮的距離標記壓縮方法[J];合肥工業(yè)大學學報(自然科學版);2006年01期

10 鄧立寶;喬立巖;俞洋;彭喜元;;基于差值二次分配的掃描鏈平衡算法[J];電子學報;2012年02期

相關會議論文 前6條

1 王飛;胡瑜;李曉維;;一種確定性掃描鏈故障診斷向量的生成方法[A];第五屆中國測試學術會議論文集[C];2008年

2 王丹;李少青;劉蓬俠;徐長明;;基于掃描的at-speed測試的設計與實現(xiàn)[A];第十五屆計算機工程與工藝年會暨第一屆微處理器技術論壇論文集（A輯）[C];2011年

3 張磊;梁華國;陶玨輝;;測試集劃分的多掃描鏈二次測試數(shù)據(jù)壓縮方法[A];計算機技術與應用進展——全國第17屆計算機科學與技術應用（CACIS）學術會議論文集（下冊）[C];2006年

4 陶玨輝;梁華國;張磊;;多掃描鏈測試集的分組標準向量壓縮法[A];第四屆中國測試學術會議論文集[C];2006年

5 羅成，

本文編號：2286818