【摘要】：由于SOC芯片方向最近幾年的快速發(fā)展,高精度、低功耗的模數(shù)轉(zhuǎn)換器芯片越來越受到重視。在此背景下,本論文是為了實(shí)現(xiàn)高精度、低功耗、寬輸入擺幅的模數(shù)轉(zhuǎn)換器。在當(dāng)前大規(guī)模集成電路工藝條件下,Sigma-Delta調(diào)制器是一種可以實(shí)現(xiàn)高分辨率模數(shù)轉(zhuǎn)換器的有效方式,由于結(jié)合過采樣、噪聲整形技術(shù),使用Sigma-Delta調(diào)制器的模數(shù)轉(zhuǎn)換器能夠?qū)崿F(xiàn)16位以上的分辨率。這種結(jié)構(gòu)不容易受到模擬電路非理想因素的影響,在當(dāng)前工藝條件下,可以相對(duì)容易實(shí)現(xiàn)低成本、高性能的模數(shù)轉(zhuǎn)換器。但Sigma-Delta ADC難以轉(zhuǎn)換高速信號(hào),而且模擬電路難度的降低增加了抽取濾波器的設(shè)計(jì)難度。本論文Sigma-Delta調(diào)制器主要從高精度、低功耗以及寬輸入擺幅這幾個(gè)方向深入研究。高階Sigma-Delta調(diào)制器需要考慮穩(wěn)定性問題,為了保證系統(tǒng)的穩(wěn)定性,本論文Sigma-Delta調(diào)制器采用2-2MASH結(jié)構(gòu)。為了減小1/f噪聲和失調(diào)噪聲,調(diào)制器第一級(jí)的積分器采用了斬波穩(wěn)定技術(shù),通過MATLAB軟件建模和系統(tǒng)仿真,得到了調(diào)制器所需的前饋因子、反饋因子和積分器增益因子,采用一組全新設(shè)計(jì)的系數(shù),使得調(diào)制器的過載輸入電平幾乎達(dá)到了滿擺幅。為了符合應(yīng)用的易攜帶型,調(diào)制器芯片采用低功耗的設(shè)計(jì)思路,從而使整個(gè)系統(tǒng)有最低功耗。通過本次設(shè)計(jì),形成了從系統(tǒng)建模、電路設(shè)計(jì)、版圖設(shè)計(jì)到流片的電路設(shè)計(jì)流程。本論文調(diào)制器采用全差分開關(guān)電容結(jié)構(gòu),采用了MXIC的0.5μm L50w CMOS工藝實(shí)現(xiàn)Sigma-Delta調(diào)制器,電源電壓為5V,仿真得到在信號(hào)帶寬為7.8KHz,采樣頻率為1MHz條件下,調(diào)制器的輸入擺幅為±4V,最高信噪比為111.3d B,有效位數(shù)約為18位,功耗約為6.6m W,該Sigma-Delta調(diào)制器適合對(duì)精度、功耗、輸入擺幅要求較高的模數(shù)轉(zhuǎn)換器。
[Abstract]:Due to the rapid development of SOC chips in recent years, high precision and low power ADC chips have attracted more and more attention. In this context, the purpose of this paper is to achieve high precision, low power consumption, wide input swing A / D converter. Sigma-Delta modulator is an effective way to realize high resolution A / D converter under the current LSI technology. The A / D converter using Sigma-Delta modulator can achieve 16 bits or more resolution. This structure is not easily affected by the non-ideal factors of analog circuits. Under the current technological conditions, it is relatively easy to achieve low-cost, high-performance analog-to-digital converters. However, it is difficult for Sigma-Delta ADC to convert high speed signal, and the difficulty of analog circuit increases the design difficulty of decimation filter. In this paper, the Sigma-Delta modulator is mainly studied in the aspects of high precision, low power consumption and wide input swing. The high order Sigma-Delta modulator needs to consider the stability problem. In order to ensure the stability of the system, the 2-2MASH structure is adopted in the Sigma-Delta modulator. In order to reduce 1 / f noise and offset noise, chopper stabilization technique is used in the integrator of the first stage of the modulator. The feedforward factor, feedback factor and integrator gain factor are obtained by MATLAB software modeling and system simulation. By using a new set of design coefficients, the overload input level of the modulator almost reaches the full swing. In order to meet the easy-to-carry application, the modulator chip uses a low power design idea, so that the whole system has the lowest power consumption. Through this design, the circuit design flow from system modeling, circuit design, layout design to chip design has been formed. In this paper, a fully differential switched capacitor (DSC) structure is adopted. The Sigma-Delta modulator is realized by using the 0.5 渭 m L50w CMOS process of MXIC. The power supply voltage is 5 V. The simulation results show that the signal bandwidth is 7.8 KHz and the sampling frequency is 1MHz. The input amplitude of the modulator is 鹵4V, the maximum signal-to-noise ratio is 111.3 dB, the effective bit number is about 18 bits and the power consumption is about 6.6 MW. The Sigma-Delta modulator is suitable for A / D converters with high precision, power consumption and input swing.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN761

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 王晉,仇玉林,田澤;全差分增益提高運(yùn)算放大器的分析與設(shè)計(jì)[J];電子器件;2005年02期

2 曹燕杰;王勇;朱琪;華夢琪;吳海宏;張勇;;IC設(shè)計(jì)中的ESD保護(hù)技術(shù)探討[J];電子與封裝;2012年12期

，

本文編號(hào)：2208565