【摘要】：碳化硅(Silicon Carbide, SiC)作為一種第三代半導體,具有禁帶寬度大、臨界擊穿電場大、熱導率大,使其特別適用于高溫高壓等領域中應用。在SiC的多種同質異型體中,4H-SiC具有較高的電子遷移率和較低的各向異性,使其更具有研究和商業(yè)價值。作為一種電流控制型器件,4H-SiC雙極型晶體管(4H-SiC BJT)具有較低的導通電阻、較低的開態(tài)損耗以及不存在二次擊穿的優(yōu)點,但目前器件仍面臨著電流增益低,長期工作下器件退化等問題,對4H-SiC BJT研究具有重要意義。本文基于二維數值分析的方法,對4H-SiC BJT進行了研究。為了得到較為準確的仿真結果,首先建立了器件仿真模型并給出了參數,其中包括雜質不完全電離模型、SRH及Auger復合模型等。其次,通過仿真分析了影響器件性能的參數,包括發(fā)射區(qū)、基區(qū)及漂移區(qū)參數對器件耐壓、導通電阻及電流增益的影響；以1200V4H-SiC BJT為目標,優(yōu)化了器件參數,最終得到了共發(fā)射極電流增益為39,比導通電阻為3.7mΩ·cm2,理想擊穿電壓為1580V的高壓4H-SiC BJT功率器件�？紤]邊緣電場集中,設計場限環(huán)和結終端擴展兩種結終端,成功降低了電場峰值,避免了邊緣電場集中現象,兩種結終端的擊穿電壓都達到了1470V左右,達到了理想平行平面結的93%。最后,針對外基區(qū)表面復合效應導致低電流增益的問題,本文從器件結構和工藝兩個方向進行了探討。在器件結構方面,提出了發(fā)射極金屬延伸和P型鈍化層兩種新型器件結構；發(fā)射極金屬延伸結構通過控制外基區(qū)表面電勢調制表面載流子濃度分布,從而降低外基區(qū)表面復合速率。通過仿真發(fā)現外基區(qū)表面復合效應明顯減弱,器件共發(fā)射極電流增益分別提高了63%。P型鈍化層新型器件結構則是通過在外基區(qū)引入高濃度P型鈍化層,使外基區(qū)電阻大大降低,通過仿真優(yōu)化后的器件共發(fā)射極電流增益提高了117%。從工藝上,通過對比不同氧化退火實驗條件下SiC/SiO2界面質量發(fā)現,NO退火確實能減小界面態(tài)密度,這與之前報道文獻一致；另外適當提高退火溫度能夠提高界面質量。
[Abstract]:As a kind of third generation semiconductor, silicon carbide (Silicon Carbide, SiC) has large band gap, large critical breakdown electric field and large thermal conductivity, which makes it especially suitable for high temperature and high pressure applications. 4H-SiC has higher electron mobility and lower anisotropy in various homotropic SiC bodies, which makes it more valuable for research and commerce. As a current-controlled device, 4H-SiC bipolar transistor (4H-SiC BJT) has the advantages of low on-resistance, low on-state loss and no secondary breakdown, but the current gain is still low. The problem of device degradation in long-term operation is of great significance to the study of 4H-SiC BJT. Based on the method of two-dimensional numerical analysis, 4H-SiC BJT is studied in this paper. In order to obtain more accurate simulation results, the device simulation model is established and the parameters are given, including impurity incomplete ionization model and Auger composite model. Secondly, the influence of the parameters of the device, including the emission region, base region and drift region, on the voltage resistance, on-resistance and current gain of the device is analyzed by simulation, and the parameters of the device are optimized with 1200V4H-SiC BJT as the target. Finally, a high voltage 4H-SiC BJT power device with a common emitter current gain of 39 and an ideal breakdown voltage of 1580V with a specific on-resistance of 3.7 m 惟 cm2, is obtained. Considering the edge electric field concentration, two kinds of junction terminals are designed, which are field limiting loop and junction terminal expansion. The peak value of electric field is reduced successfully, and the phenomenon of edge electric field concentration is avoided. The breakdown voltage of both junction terminals is about 1470V. The ideal parallel plane junction is reached at 933. Finally, aiming at the problem of low current gain caused by the surface recombination effect in the outer base region, the structure and process of the device are discussed in this paper. In terms of device structure, two new device structures, emitter metal extension and P-type passivating layer, are proposed, which modulate the surface carrier concentration distribution by controlling the surface potential of the external base region. Thus, the surface recombination rate of the outer base region is reduced. The simulation results show that the surface recombination effect of the outer base region is obviously weakened, and the common emitter current gain of the device is increased by 63. P passivating layer. The new device structure is based on the introduction of high concentration P passivation layer in the outer base region, which greatly reduces the external base resistance. The emitter current gain is improved by simulation. From the process point of view, by comparing the interfacial quality of SiC/SiO2 under different oxidation annealing conditions, it is found that the interfacial state density can be reduced by annealing with no, which is consistent with the previous reports, and the interfacial quality can be improved by increasing annealing temperature appropriately.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN322.8

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